
pet_recycl.elf:     file format elf32-littlearm

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .isr_vector   0000010c  08000000  08000000  00010000  2**0
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  1 .text         0000274c  0800010c  0800010c  0001010c  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  2 .rodata       00002130  08002858  08002858  00012858  2**2
                  CONTENTS, ALLOC, LOAD, READONLY, DATA
  3 .ARM.extab    00000000  08004988  08004988  0002001c  2**0
                  CONTENTS
  4 .ARM          00000000  08004988  08004988  0002001c  2**0
                  CONTENTS
  5 .preinit_array 00000000  08004988  08004988  0002001c  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  6 .init_array   00000004  08004988  08004988  00014988  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  7 .fini_array   00000004  0800498c  0800498c  0001498c  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  8 .data         0000001c  20000000  08004990  00020000  2**2
                  CONTENTS, ALLOC, LOAD, DATA
  9 .bss          00000484  2000001c  080049ac  0002001c  2**2
                  ALLOC
 10 ._user_heap_stack 00000600  200004a0  080049ac  000204a0  2**0
                  ALLOC
 11 .ARM.attributes 00000029  00000000  00000000  0002001c  2**0
                  CONTENTS, READONLY
 12 .comment      00000043  00000000  00000000  00020045  2**0
                  CONTENTS, READONLY
 13 .debug_info   0000747f  00000000  00000000  00020088  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 14 .debug_abbrev 000016cb  00000000  00000000  00027507  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 15 .debug_aranges 000007e8  00000000  00000000  00028bd8  2**3
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 16 .debug_rnglists 00000610  00000000  00000000  000293c0  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 17 .debug_macro  0001767d  00000000  00000000  000299d0  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 18 .debug_line   00009c76  00000000  00000000  0004104d  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 19 .debug_str    00088d5a  00000000  00000000  0004acc3  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 20 .debug_frame  00001fec  00000000  00000000  000d3a20  2**2
                  CONTENTS, READONLY, DEBUGGING, OCTETS
 21 .debug_line_str 00000066  00000000  00000000  000d5a0c  2**0
                  CONTENTS, READONLY, DEBUGGING, OCTETS

Disassembly of section .text:

0800010c <__do_global_dtors_aux>:
 800010c:	b510      	push	{r4, lr}
 800010e:	4c05      	ldr	r4, [pc, #20]	; (8000124 <__do_global_dtors_aux+0x18>)
 8000110:	7823      	ldrb	r3, [r4, #0]
 8000112:	b933      	cbnz	r3, 8000122 <__do_global_dtors_aux+0x16>
 8000114:	4b04      	ldr	r3, [pc, #16]	; (8000128 <__do_global_dtors_aux+0x1c>)
 8000116:	b113      	cbz	r3, 800011e <__do_global_dtors_aux+0x12>
 8000118:	4804      	ldr	r0, [pc, #16]	; (800012c <__do_global_dtors_aux+0x20>)
 800011a:	f3af 8000 	nop.w
 800011e:	2301      	movs	r3, #1
 8000120:	7023      	strb	r3, [r4, #0]
 8000122:	bd10      	pop	{r4, pc}
 8000124:	2000001c 	.word	0x2000001c
 8000128:	00000000 	.word	0x00000000
 800012c:	08002840 	.word	0x08002840

08000130 <frame_dummy>:
 8000130:	b508      	push	{r3, lr}
 8000132:	4b03      	ldr	r3, [pc, #12]	; (8000140 <frame_dummy+0x10>)
 8000134:	b11b      	cbz	r3, 800013e <frame_dummy+0xe>
 8000136:	4903      	ldr	r1, [pc, #12]	; (8000144 <frame_dummy+0x14>)
 8000138:	4803      	ldr	r0, [pc, #12]	; (8000148 <frame_dummy+0x18>)
 800013a:	f3af 8000 	nop.w
 800013e:	bd08      	pop	{r3, pc}
 8000140:	00000000 	.word	0x00000000
 8000144:	20000020 	.word	0x20000020
 8000148:	08002840 	.word	0x08002840

0800014c <main>:
/**
  * @brief  The application entry point.
  * @retval int
  */
int main(void)
{
 800014c:	b580      	push	{r7, lr}
 800014e:	af00      	add	r7, sp, #0
  /* MCU Configuration--------------------------------------------------------*/

  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
  HAL_Init();
 8000150:	f000 fe3a 	bl	8000dc8 <HAL_Init>

  /* Configure the system clock */
  SystemClock_Config();
 8000154:	f000 f900 	bl	8000358 <SystemClock_Config>

  /* Initialize all configured peripherals */
  GPIO_Init();
 8000158:	f000 f9d0 	bl	80004fc <GPIO_Init>
  TIM2_Init();		//encoder
 800015c:	f000 f970 	bl	8000440 <TIM2_Init>
  TIM3_Init();		//pwm
 8000160:	f000 f996 	bl	8000490 <TIM3_Init>
  MX_I2C1_Init();	//lcd
 8000164:	f000 f93e 	bl	80003e4 <MX_I2C1_Init>
  SSD1306_Init();
 8000168:	f000 fab6 	bl	80006d8 <SSD1306_Init>
  ADC_Init();
 800016c:	f000 fa56 	bl	800061c <ADC_Init>
  void TIM3_IRQHandler(void){
	 TIM3->SR &= TIM_SR_UIF;
 }
 */

  showGreetings();
 8000170:	f000 f898 	bl	80002a4 <showGreetings>
  SSD1306_Clear();
 8000174:	f000 fcd3 	bl	8000b1e <SSD1306_Clear>

  /* Infinite loop */
  while(1){

	  if(((GPIOC->IDR >> 14) & 0x01))
 8000178:	4b17      	ldr	r3, [pc, #92]	; (80001d8 <main+0x8c>)
 800017a:	689b      	ldr	r3, [r3, #8]
 800017c:	f403 4380 	and.w	r3, r3, #16384	; 0x4000
 8000180:	2b00      	cmp	r3, #0
 8000182:	d004      	beq.n	800018e <main+0x42>
		  GPIOC->BSRR = GPIO_BSRR_BS13;
 8000184:	4b14      	ldr	r3, [pc, #80]	; (80001d8 <main+0x8c>)
 8000186:	f44f 5200 	mov.w	r2, #8192	; 0x2000
 800018a:	611a      	str	r2, [r3, #16]
 800018c:	e003      	b.n	8000196 <main+0x4a>
	  else
		  GPIOC->BSRR = GPIO_BSRR_BR13;
 800018e:	4b12      	ldr	r3, [pc, #72]	; (80001d8 <main+0x8c>)
 8000190:	f04f 5200 	mov.w	r2, #536870912	; 0x20000000
 8000194:	611a      	str	r2, [r3, #16]

	  cnt = TIM2->CNT;
 8000196:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
 800019a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 800019c:	4a0f      	ldr	r2, [pc, #60]	; (80001dc <main+0x90>)
 800019e:	6013      	str	r3, [r2, #0]
	  adc = get_ADC_value();
 80001a0:	f000 f8c2 	bl	8000328 <get_ADC_value>
 80001a4:	4603      	mov	r3, r0
 80001a6:	461a      	mov	r2, r3
 80001a8:	4b0d      	ldr	r3, [pc, #52]	; (80001e0 <main+0x94>)
 80001aa:	601a      	str	r2, [r3, #0]
	  //timer = TIM3->CNT;

	  TIM3->CCR1 = cnt;
 80001ac:	4a0d      	ldr	r2, [pc, #52]	; (80001e4 <main+0x98>)
 80001ae:	4b0b      	ldr	r3, [pc, #44]	; (80001dc <main+0x90>)
 80001b0:	681b      	ldr	r3, [r3, #0]
 80001b2:	6353      	str	r3, [r2, #52]	; 0x34
	  TIM3->CCR2 = adc/40;
 80001b4:	4b0a      	ldr	r3, [pc, #40]	; (80001e0 <main+0x94>)
 80001b6:	681b      	ldr	r3, [r3, #0]
 80001b8:	4a0a      	ldr	r2, [pc, #40]	; (80001e4 <main+0x98>)
 80001ba:	490b      	ldr	r1, [pc, #44]	; (80001e8 <main+0x9c>)
 80001bc:	fba1 1303 	umull	r1, r3, r1, r3
 80001c0:	095b      	lsrs	r3, r3, #5
 80001c2:	6393      	str	r3, [r2, #56]	; 0x38

	  showData(cnt, adc);
 80001c4:	4b05      	ldr	r3, [pc, #20]	; (80001dc <main+0x90>)
 80001c6:	681b      	ldr	r3, [r3, #0]
 80001c8:	4a05      	ldr	r2, [pc, #20]	; (80001e0 <main+0x94>)
 80001ca:	6812      	ldr	r2, [r2, #0]
 80001cc:	4611      	mov	r1, r2
 80001ce:	4618      	mov	r0, r3
 80001d0:	f000 f80c 	bl	80001ec <showData>
	  if(((GPIOC->IDR >> 14) & 0x01))
 80001d4:	e7d0      	b.n	8000178 <main+0x2c>
 80001d6:	bf00      	nop
 80001d8:	40011000 	.word	0x40011000
 80001dc:	2000008c 	.word	0x2000008c
 80001e0:	20000090 	.word	0x20000090
 80001e4:	40000400 	.word	0x40000400
 80001e8:	cccccccd 	.word	0xcccccccd

080001ec <showData>:
/**
  * @brief Show parameters
  * @param None
  * @retval None
  */
void showData(uint32_t cnt_value, uint32_t adc_value){
 80001ec:	b580      	push	{r7, lr}
 80001ee:	b086      	sub	sp, #24
 80001f0:	af00      	add	r7, sp, #0
 80001f2:	6078      	str	r0, [r7, #4]
 80001f4:	6039      	str	r1, [r7, #0]

	char cnt_temp[5];
	char adc_temp[5];
	itoa(cnt_value, cnt_temp, 10);
 80001f6:	687b      	ldr	r3, [r7, #4]
 80001f8:	f107 0110 	add.w	r1, r7, #16
 80001fc:	220a      	movs	r2, #10
 80001fe:	4618      	mov	r0, r3
 8000200:	f002 faae 	bl	8002760 <itoa>
	itoa(adc_value, adc_temp, 10);
 8000204:	683b      	ldr	r3, [r7, #0]
 8000206:	f107 0108 	add.w	r1, r7, #8
 800020a:	220a      	movs	r2, #10
 800020c:	4618      	mov	r0, r3
 800020e:	f002 faa7 	bl	8002760 <itoa>

	//clear lcd
	SSD1306_GotoXY (44,0);
 8000212:	2100      	movs	r1, #0
 8000214:	202c      	movs	r0, #44	; 0x2c
 8000216:	f000 fbc7 	bl	80009a8 <SSD1306_GotoXY>
	SSD1306_Puts ("     ", &Font_11x18, 1);
 800021a:	2201      	movs	r2, #1
 800021c:	491d      	ldr	r1, [pc, #116]	; (8000294 <showData+0xa8>)
 800021e:	481e      	ldr	r0, [pc, #120]	; (8000298 <showData+0xac>)
 8000220:	f000 fc58 	bl	8000ad4 <SSD1306_Puts>
	SSD1306_GotoXY (44,32);
 8000224:	2120      	movs	r1, #32
 8000226:	202c      	movs	r0, #44	; 0x2c
 8000228:	f000 fbbe 	bl	80009a8 <SSD1306_GotoXY>
	SSD1306_Puts ("     ", &Font_11x18, 1);
 800022c:	2201      	movs	r2, #1
 800022e:	4919      	ldr	r1, [pc, #100]	; (8000294 <showData+0xa8>)
 8000230:	4819      	ldr	r0, [pc, #100]	; (8000298 <showData+0xac>)
 8000232:	f000 fc4f 	bl	8000ad4 <SSD1306_Puts>

	SSD1306_GotoXY (0,0);
 8000236:	2100      	movs	r1, #0
 8000238:	2000      	movs	r0, #0
 800023a:	f000 fbb5 	bl	80009a8 <SSD1306_GotoXY>
	SSD1306_Puts ("cnt=", &Font_11x18, 1);
 800023e:	2201      	movs	r2, #1
 8000240:	4914      	ldr	r1, [pc, #80]	; (8000294 <showData+0xa8>)
 8000242:	4816      	ldr	r0, [pc, #88]	; (800029c <showData+0xb0>)
 8000244:	f000 fc46 	bl	8000ad4 <SSD1306_Puts>

	SSD1306_GotoXY (44,0);
 8000248:	2100      	movs	r1, #0
 800024a:	202c      	movs	r0, #44	; 0x2c
 800024c:	f000 fbac 	bl	80009a8 <SSD1306_GotoXY>
	SSD1306_Puts (cnt_temp, &Font_11x18, 1);
 8000250:	f107 0310 	add.w	r3, r7, #16
 8000254:	2201      	movs	r2, #1
 8000256:	490f      	ldr	r1, [pc, #60]	; (8000294 <showData+0xa8>)
 8000258:	4618      	mov	r0, r3
 800025a:	f000 fc3b 	bl	8000ad4 <SSD1306_Puts>

	SSD1306_GotoXY (0, 32);
 800025e:	2120      	movs	r1, #32
 8000260:	2000      	movs	r0, #0
 8000262:	f000 fba1 	bl	80009a8 <SSD1306_GotoXY>
	SSD1306_Puts ("adc=", &Font_11x18, 1);
 8000266:	2201      	movs	r2, #1
 8000268:	490a      	ldr	r1, [pc, #40]	; (8000294 <showData+0xa8>)
 800026a:	480d      	ldr	r0, [pc, #52]	; (80002a0 <showData+0xb4>)
 800026c:	f000 fc32 	bl	8000ad4 <SSD1306_Puts>

	SSD1306_GotoXY (44,32);
 8000270:	2120      	movs	r1, #32
 8000272:	202c      	movs	r0, #44	; 0x2c
 8000274:	f000 fb98 	bl	80009a8 <SSD1306_GotoXY>
	SSD1306_Puts (adc_temp, &Font_11x18, 1);
 8000278:	f107 0308 	add.w	r3, r7, #8
 800027c:	2201      	movs	r2, #1
 800027e:	4905      	ldr	r1, [pc, #20]	; (8000294 <showData+0xa8>)
 8000280:	4618      	mov	r0, r3
 8000282:	f000 fc27 	bl	8000ad4 <SSD1306_Puts>

	SSD1306_UpdateScreen();
 8000286:	f000 faeb 	bl	8000860 <SSD1306_UpdateScreen>
}
 800028a:	bf00      	nop
 800028c:	3718      	adds	r7, #24
 800028e:	46bd      	mov	sp, r7
 8000290:	bd80      	pop	{r7, pc}
 8000292:	bf00      	nop
 8000294:	20000000 	.word	0x20000000
 8000298:	08002858 	.word	0x08002858
 800029c:	08002860 	.word	0x08002860
 80002a0:	08002868 	.word	0x08002868

080002a4 <showGreetings>:
/**
  * @brief Show greetings and logo
  * @param None
  * @retval None
  */
void showGreetings(){
 80002a4:	b580      	push	{r7, lr}
 80002a6:	af00      	add	r7, sp, #0
  SSD1306_Clear();
 80002a8:	f000 fc39 	bl	8000b1e <SSD1306_Clear>
  SSD1306_GotoXY (0,0);
 80002ac:	2100      	movs	r1, #0
 80002ae:	2000      	movs	r0, #0
 80002b0:	f000 fb7a 	bl	80009a8 <SSD1306_GotoXY>
  SSD1306_Puts ("PET", &Font_16x26, 1);
 80002b4:	2201      	movs	r2, #1
 80002b6:	4917      	ldr	r1, [pc, #92]	; (8000314 <showGreetings+0x70>)
 80002b8:	4817      	ldr	r0, [pc, #92]	; (8000318 <showGreetings+0x74>)
 80002ba:	f000 fc0b 	bl	8000ad4 <SSD1306_Puts>
  SSD1306_GotoXY (0, 32);
 80002be:	2120      	movs	r1, #32
 80002c0:	2000      	movs	r0, #0
 80002c2:	f000 fb71 	bl	80009a8 <SSD1306_GotoXY>
  SSD1306_Puts ("RECYCLER", &Font_16x26, 1);
 80002c6:	2201      	movs	r2, #1
 80002c8:	4912      	ldr	r1, [pc, #72]	; (8000314 <showGreetings+0x70>)
 80002ca:	4814      	ldr	r0, [pc, #80]	; (800031c <showGreetings+0x78>)
 80002cc:	f000 fc02 	bl	8000ad4 <SSD1306_Puts>
  SSD1306_UpdateScreen();
 80002d0:	f000 fac6 	bl	8000860 <SSD1306_UpdateScreen>
  HAL_Delay(1000);
 80002d4:	f44f 707a 	mov.w	r0, #1000	; 0x3e8
 80002d8:	f000 fdd8 	bl	8000e8c <HAL_Delay>
  SSD1306_Clear();
 80002dc:	f000 fc1f 	bl	8000b1e <SSD1306_Clear>
  SSD1306_GotoXY (0,0);
 80002e0:	2100      	movs	r1, #0
 80002e2:	2000      	movs	r0, #0
 80002e4:	f000 fb60 	bl	80009a8 <SSD1306_GotoXY>
  SSD1306_Puts ("by John", &Font_16x26, 1);
 80002e8:	2201      	movs	r2, #1
 80002ea:	490a      	ldr	r1, [pc, #40]	; (8000314 <showGreetings+0x70>)
 80002ec:	480c      	ldr	r0, [pc, #48]	; (8000320 <showGreetings+0x7c>)
 80002ee:	f000 fbf1 	bl	8000ad4 <SSD1306_Puts>
  SSD1306_GotoXY (0, 32);
 80002f2:	2120      	movs	r1, #32
 80002f4:	2000      	movs	r0, #0
 80002f6:	f000 fb57 	bl	80009a8 <SSD1306_GotoXY>
  //SSD1306_Puts ("XXXXXXXXXXXXXX", &Font_11x18, 1);
  SSD1306_Puts ("   Pank", &Font_16x26, 1);
 80002fa:	2201      	movs	r2, #1
 80002fc:	4905      	ldr	r1, [pc, #20]	; (8000314 <showGreetings+0x70>)
 80002fe:	4809      	ldr	r0, [pc, #36]	; (8000324 <showGreetings+0x80>)
 8000300:	f000 fbe8 	bl	8000ad4 <SSD1306_Puts>
  SSD1306_UpdateScreen();
 8000304:	f000 faac 	bl	8000860 <SSD1306_UpdateScreen>
  HAL_Delay(1000);
 8000308:	f44f 707a 	mov.w	r0, #1000	; 0x3e8
 800030c:	f000 fdbe 	bl	8000e8c <HAL_Delay>
}
 8000310:	bf00      	nop
 8000312:	bd80      	pop	{r7, pc}
 8000314:	20000008 	.word	0x20000008
 8000318:	08002870 	.word	0x08002870
 800031c:	08002874 	.word	0x08002874
 8000320:	08002880 	.word	0x08002880
 8000324:	08002888 	.word	0x08002888

08000328 <get_ADC_value>:
/**
  * @brief ADC Initialization Function
  * @param None
  * @retval uint 16_t adc value
  */
uint16_t get_ADC_value(void){
 8000328:	b480      	push	{r7}
 800032a:	af00      	add	r7, sp, #0

	ADC1->CR2 |= ADC_CR2_SWSTART;	//start conversion
 800032c:	4b09      	ldr	r3, [pc, #36]	; (8000354 <get_ADC_value+0x2c>)
 800032e:	689b      	ldr	r3, [r3, #8]
 8000330:	4a08      	ldr	r2, [pc, #32]	; (8000354 <get_ADC_value+0x2c>)
 8000332:	f443 0380 	orr.w	r3, r3, #4194304	; 0x400000
 8000336:	6093      	str	r3, [r2, #8]
	while(!(ADC1->SR & ADC_SR_EOC)){} 	//wait conversion result
 8000338:	bf00      	nop
 800033a:	4b06      	ldr	r3, [pc, #24]	; (8000354 <get_ADC_value+0x2c>)
 800033c:	681b      	ldr	r3, [r3, #0]
 800033e:	f003 0302 	and.w	r3, r3, #2
 8000342:	2b00      	cmp	r3, #0
 8000344:	d0f9      	beq.n	800033a <get_ADC_value+0x12>

	return ADC1->DR;
 8000346:	4b03      	ldr	r3, [pc, #12]	; (8000354 <get_ADC_value+0x2c>)
 8000348:	6cdb      	ldr	r3, [r3, #76]	; 0x4c
 800034a:	b29b      	uxth	r3, r3
}
 800034c:	4618      	mov	r0, r3
 800034e:	46bd      	mov	sp, r7
 8000350:	bc80      	pop	{r7}
 8000352:	4770      	bx	lr
 8000354:	40012400 	.word	0x40012400

08000358 <SystemClock_Config>:
/**
  * @brief System Clock Configuration
  * @retval None
  */
void SystemClock_Config(void)
{
 8000358:	b580      	push	{r7, lr}
 800035a:	b090      	sub	sp, #64	; 0x40
 800035c:	af00      	add	r7, sp, #0
	RCC_OscInitTypeDef RCC_OscInitStruct = {0};
 800035e:	f107 0318 	add.w	r3, r7, #24
 8000362:	2228      	movs	r2, #40	; 0x28
 8000364:	2100      	movs	r1, #0
 8000366:	4618      	mov	r0, r3
 8000368:	f002 fa3e 	bl	80027e8 <memset>
	RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 800036c:	1d3b      	adds	r3, r7, #4
 800036e:	2200      	movs	r2, #0
 8000370:	601a      	str	r2, [r3, #0]
 8000372:	605a      	str	r2, [r3, #4]
 8000374:	609a      	str	r2, [r3, #8]
 8000376:	60da      	str	r2, [r3, #12]
 8000378:	611a      	str	r2, [r3, #16]

	/** Initializes the RCC Oscillators according to the specified parameters
	  * in the RCC_OscInitTypeDef structure.
	  */
	RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
 800037a:	2301      	movs	r3, #1
 800037c:	61bb      	str	r3, [r7, #24]
	RCC_OscInitStruct.HSEState = RCC_HSE_ON;
 800037e:	f44f 3380 	mov.w	r3, #65536	; 0x10000
 8000382:	61fb      	str	r3, [r7, #28]
	RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
 8000384:	2300      	movs	r3, #0
 8000386:	623b      	str	r3, [r7, #32]
	RCC_OscInitStruct.HSIState = RCC_HSI_ON;
 8000388:	2301      	movs	r3, #1
 800038a:	62bb      	str	r3, [r7, #40]	; 0x28
	RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
 800038c:	2302      	movs	r3, #2
 800038e:	637b      	str	r3, [r7, #52]	; 0x34
	RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
 8000390:	f44f 3380 	mov.w	r3, #65536	; 0x10000
 8000394:	63bb      	str	r3, [r7, #56]	; 0x38
	RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9;
 8000396:	f44f 13e0 	mov.w	r3, #1835008	; 0x1c0000
 800039a:	63fb      	str	r3, [r7, #60]	; 0x3c
	if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
 800039c:	f107 0318 	add.w	r3, r7, #24
 80003a0:	4618      	mov	r0, r3
 80003a2:	f001 fdc9 	bl	8001f38 <HAL_RCC_OscConfig>
 80003a6:	4603      	mov	r3, r0
 80003a8:	2b00      	cmp	r3, #0
 80003aa:	d001      	beq.n	80003b0 <SystemClock_Config+0x58>
	{
	  Error_Handler();
 80003ac:	f000 f98e 	bl	80006cc <Error_Handler>
	}

	/** Initializes the CPU, AHB and APB buses clocks
	*/
	RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
 80003b0:	230f      	movs	r3, #15
 80003b2:	607b      	str	r3, [r7, #4]
	                            |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
	RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
 80003b4:	2302      	movs	r3, #2
 80003b6:	60bb      	str	r3, [r7, #8]
	RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
 80003b8:	2300      	movs	r3, #0
 80003ba:	60fb      	str	r3, [r7, #12]
	RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2;
 80003bc:	f44f 6380 	mov.w	r3, #1024	; 0x400
 80003c0:	613b      	str	r3, [r7, #16]
	RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 80003c2:	2300      	movs	r3, #0
 80003c4:	617b      	str	r3, [r7, #20]

	if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK)
 80003c6:	1d3b      	adds	r3, r7, #4
 80003c8:	2102      	movs	r1, #2
 80003ca:	4618      	mov	r0, r3
 80003cc:	f002 f836 	bl	800243c <HAL_RCC_ClockConfig>
 80003d0:	4603      	mov	r3, r0
 80003d2:	2b00      	cmp	r3, #0
 80003d4:	d001      	beq.n	80003da <SystemClock_Config+0x82>
	{
	  Error_Handler();
 80003d6:	f000 f979 	bl	80006cc <Error_Handler>
	}
}
 80003da:	bf00      	nop
 80003dc:	3740      	adds	r7, #64	; 0x40
 80003de:	46bd      	mov	sp, r7
 80003e0:	bd80      	pop	{r7, pc}
	...

080003e4 <MX_I2C1_Init>:
  * @brief I2C2 Initialization Function
  * @param None
  * @retval None
  */
static void MX_I2C1_Init(void)
{
 80003e4:	b580      	push	{r7, lr}
 80003e6:	af00      	add	r7, sp, #0
  /* USER CODE END I2C1_Init 0 */

  /* USER CODE BEGIN I2C1_Init 1 */

  /* USER CODE END I2C1_Init 1 */
  hi2c1.Instance = I2C1;
 80003e8:	4b12      	ldr	r3, [pc, #72]	; (8000434 <MX_I2C1_Init+0x50>)
 80003ea:	4a13      	ldr	r2, [pc, #76]	; (8000438 <MX_I2C1_Init+0x54>)
 80003ec:	601a      	str	r2, [r3, #0]
  hi2c1.Init.ClockSpeed = 400000;
 80003ee:	4b11      	ldr	r3, [pc, #68]	; (8000434 <MX_I2C1_Init+0x50>)
 80003f0:	4a12      	ldr	r2, [pc, #72]	; (800043c <MX_I2C1_Init+0x58>)
 80003f2:	605a      	str	r2, [r3, #4]
  hi2c1.Init.DutyCycle = I2C_DUTYCYCLE_2;
 80003f4:	4b0f      	ldr	r3, [pc, #60]	; (8000434 <MX_I2C1_Init+0x50>)
 80003f6:	2200      	movs	r2, #0
 80003f8:	609a      	str	r2, [r3, #8]
  hi2c1.Init.OwnAddress1 = 0;
 80003fa:	4b0e      	ldr	r3, [pc, #56]	; (8000434 <MX_I2C1_Init+0x50>)
 80003fc:	2200      	movs	r2, #0
 80003fe:	60da      	str	r2, [r3, #12]
  hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
 8000400:	4b0c      	ldr	r3, [pc, #48]	; (8000434 <MX_I2C1_Init+0x50>)
 8000402:	f44f 4280 	mov.w	r2, #16384	; 0x4000
 8000406:	611a      	str	r2, [r3, #16]
  hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
 8000408:	4b0a      	ldr	r3, [pc, #40]	; (8000434 <MX_I2C1_Init+0x50>)
 800040a:	2200      	movs	r2, #0
 800040c:	615a      	str	r2, [r3, #20]
  hi2c1.Init.OwnAddress2 = 0;
 800040e:	4b09      	ldr	r3, [pc, #36]	; (8000434 <MX_I2C1_Init+0x50>)
 8000410:	2200      	movs	r2, #0
 8000412:	619a      	str	r2, [r3, #24]
  hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
 8000414:	4b07      	ldr	r3, [pc, #28]	; (8000434 <MX_I2C1_Init+0x50>)
 8000416:	2200      	movs	r2, #0
 8000418:	61da      	str	r2, [r3, #28]
  hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
 800041a:	4b06      	ldr	r3, [pc, #24]	; (8000434 <MX_I2C1_Init+0x50>)
 800041c:	2200      	movs	r2, #0
 800041e:	621a      	str	r2, [r3, #32]
  if (HAL_I2C_Init(&hi2c1) != HAL_OK)
 8000420:	4804      	ldr	r0, [pc, #16]	; (8000434 <MX_I2C1_Init+0x50>)
 8000422:	f000 ffbf 	bl	80013a4 <HAL_I2C_Init>
 8000426:	4603      	mov	r3, r0
 8000428:	2b00      	cmp	r3, #0
 800042a:	d001      	beq.n	8000430 <MX_I2C1_Init+0x4c>
  {
    Error_Handler();
 800042c:	f000 f94e 	bl	80006cc <Error_Handler>
  }
  /* USER CODE BEGIN I2C1_Init 2 */

  /* USER CODE END I2C1_Init 2 */

}
 8000430:	bf00      	nop
 8000432:	bd80      	pop	{r7, pc}
 8000434:	20000038 	.word	0x20000038
 8000438:	40005400 	.word	0x40005400
 800043c:	00061a80 	.word	0x00061a80

08000440 <TIM2_Init>:
/**
  * @brief TIM2 Initialization Function (Encoder mode). Encoder connect to PA0 and PA1
  * @param None
  * @retval None
  */
static void TIM2_Init(void){
 8000440:	b480      	push	{r7}
 8000442:	af00      	add	r7, sp, #0

	//конфигурация таймера2 для энкодера
	RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;                   //тактирование таймера4
 8000444:	4b11      	ldr	r3, [pc, #68]	; (800048c <TIM2_Init+0x4c>)
 8000446:	69db      	ldr	r3, [r3, #28]
 8000448:	4a10      	ldr	r2, [pc, #64]	; (800048c <TIM2_Init+0x4c>)
 800044a:	f043 0301 	orr.w	r3, r3, #1
 800044e:	61d3      	str	r3, [r2, #28]
	TIM2->CCMR1   = TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;  //полярность сигнала для каждого входа
 8000450:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
 8000454:	f240 1201 	movw	r2, #257	; 0x101
 8000458:	619a      	str	r2, [r3, #24]
	TIM2->CCER    = TIM_CCER_CC1P | TIM_CCER_CC2P;
 800045a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
 800045e:	2222      	movs	r2, #34	; 0x22
 8000460:	621a      	str	r2, [r3, #32]
	TIM2->SMCR    = TIM_SMCR_SMS_0 | TIM_SMCR_SMS_1;      //режим энкодера
 8000462:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
 8000466:	2203      	movs	r2, #3
 8000468:	609a      	str	r2, [r3, #8]
	TIM2->ARR     = 80;                                   //значение, до которого считает CNT
 800046a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
 800046e:	2250      	movs	r2, #80	; 0x50
 8000470:	62da      	str	r2, [r3, #44]	; 0x2c
	TIM2->CNT     = 0;                                    //начальное значение счётчика
 8000472:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
 8000476:	2200      	movs	r2, #0
 8000478:	625a      	str	r2, [r3, #36]	; 0x24
	TIM2->CR1     = TIM_CR1_CEN;                          //включаем таймер
 800047a:	f04f 4380 	mov.w	r3, #1073741824	; 0x40000000
 800047e:	2201      	movs	r2, #1
 8000480:	601a      	str	r2, [r3, #0]
}
 8000482:	bf00      	nop
 8000484:	46bd      	mov	sp, r7
 8000486:	bc80      	pop	{r7}
 8000488:	4770      	bx	lr
 800048a:	bf00      	nop
 800048c:	40021000 	.word	0x40021000

08000490 <TIM3_Init>:
/**
  * @brief TIM3 Initialization Function (2 PWM channel 1-2). PWM on PA6 and PA7
  * @param None
  * @retval None
  */
static void TIM3_Init(void){
 8000490:	b480      	push	{r7}
 8000492:	af00      	add	r7, sp, #0


	  RCC->APB1ENR  |= RCC_APB1ENR_TIM3EN;                                // Включаем тактирование таймера
 8000494:	4b17      	ldr	r3, [pc, #92]	; (80004f4 <TIM3_Init+0x64>)
 8000496:	69db      	ldr	r3, [r3, #28]
 8000498:	4a16      	ldr	r2, [pc, #88]	; (80004f4 <TIM3_Init+0x64>)
 800049a:	f043 0302 	orr.w	r3, r3, #2
 800049e:	61d3      	str	r3, [r2, #28]
	  TIM3->PSC     = 7199;                                              // При тактовой частоте 72 МГц, тактирование таймера 10КГц
 80004a0:	4b15      	ldr	r3, [pc, #84]	; (80004f8 <TIM3_Init+0x68>)
 80004a2:	f641 421f 	movw	r2, #7199	; 0x1c1f
 80004a6:	629a      	str	r2, [r3, #40]	; 0x28
	  TIM3->ARR     = 100;                                               // Период ШИМ. Тактовая частота ШИМ будет равняться 10 000/100=100Гц
 80004a8:	4b13      	ldr	r3, [pc, #76]	; (80004f8 <TIM3_Init+0x68>)
 80004aa:	2264      	movs	r2, #100	; 0x64
 80004ac:	62da      	str	r2, [r3, #44]	; 0x2c
	  TIM3->CCMR1   |= (0b110 << TIM_CCMR1_OC1M_Pos);                     // Включаем PWM первого типа ch1
 80004ae:	4b12      	ldr	r3, [pc, #72]	; (80004f8 <TIM3_Init+0x68>)
 80004b0:	699b      	ldr	r3, [r3, #24]
 80004b2:	4a11      	ldr	r2, [pc, #68]	; (80004f8 <TIM3_Init+0x68>)
 80004b4:	f043 0360 	orr.w	r3, r3, #96	; 0x60
 80004b8:	6193      	str	r3, [r2, #24]
	  TIM3->CCMR1   |= (0b110 << TIM_CCMR1_OC2M_Pos);                     // Включаем PWM первого типа ch2
 80004ba:	4b0f      	ldr	r3, [pc, #60]	; (80004f8 <TIM3_Init+0x68>)
 80004bc:	699b      	ldr	r3, [r3, #24]
 80004be:	4a0e      	ldr	r2, [pc, #56]	; (80004f8 <TIM3_Init+0x68>)
 80004c0:	f443 43c0 	orr.w	r3, r3, #24576	; 0x6000
 80004c4:	6193      	str	r3, [r2, #24]
	  TIM3->CCER    |= (TIM_CCER_CC1E | TIM_CCER_CC2E);                                     // Разрешаем первому and 2 каналу плеваться на выход
 80004c6:	4b0c      	ldr	r3, [pc, #48]	; (80004f8 <TIM3_Init+0x68>)
 80004c8:	6a1b      	ldr	r3, [r3, #32]
 80004ca:	4a0b      	ldr	r2, [pc, #44]	; (80004f8 <TIM3_Init+0x68>)
 80004cc:	f043 0311 	orr.w	r3, r3, #17
 80004d0:	6213      	str	r3, [r2, #32]
	  TIM3->CR1     |= TIM_CR1_CEN;                                       // Включаем таймер
 80004d2:	4b09      	ldr	r3, [pc, #36]	; (80004f8 <TIM3_Init+0x68>)
 80004d4:	681b      	ldr	r3, [r3, #0]
 80004d6:	4a08      	ldr	r2, [pc, #32]	; (80004f8 <TIM3_Init+0x68>)
 80004d8:	f043 0301 	orr.w	r3, r3, #1
 80004dc:	6013      	str	r3, [r2, #0]

	  TIM3->CCR1    = 0;                                                // Коэффициент заполнения ШИМ 0% (При таких значениях делителей).
 80004de:	4b06      	ldr	r3, [pc, #24]	; (80004f8 <TIM3_Init+0x68>)
 80004e0:	2200      	movs	r2, #0
 80004e2:	635a      	str	r2, [r3, #52]	; 0x34
	  TIM3->CCR2    = 0;                                                // Коэффициент заполнения ШИМ 0% (При таких значениях делителей).
 80004e4:	4b04      	ldr	r3, [pc, #16]	; (80004f8 <TIM3_Init+0x68>)
 80004e6:	2200      	movs	r2, #0
 80004e8:	639a      	str	r2, [r3, #56]	; 0x38
	  /*
	   * С этого момента на выводе PA0 должен появиться ШИМ
	   */
}
 80004ea:	bf00      	nop
 80004ec:	46bd      	mov	sp, r7
 80004ee:	bc80      	pop	{r7}
 80004f0:	4770      	bx	lr
 80004f2:	bf00      	nop
 80004f4:	40021000 	.word	0x40021000
 80004f8:	40000400 	.word	0x40000400

080004fc <GPIO_Init>:
  * @brief GPIO Initialization Function
  * @param None
  * @retval None
  */
static void GPIO_Init(void)
{
 80004fc:	b480      	push	{r7}
 80004fe:	af00      	add	r7, sp, #0

	//enable port A
	RCC->APB2ENR |= RCC_APB2ENR_IOPAEN;
 8000500:	4b43      	ldr	r3, [pc, #268]	; (8000610 <GPIO_Init+0x114>)
 8000502:	699b      	ldr	r3, [r3, #24]
 8000504:	4a42      	ldr	r2, [pc, #264]	; (8000610 <GPIO_Init+0x114>)
 8000506:	f043 0304 	orr.w	r3, r3, #4
 800050a:	6193      	str	r3, [r2, #24]

	//enable port B
	RCC->APB2ENR |= RCC_APB2ENR_IOPBEN;
 800050c:	4b40      	ldr	r3, [pc, #256]	; (8000610 <GPIO_Init+0x114>)
 800050e:	699b      	ldr	r3, [r3, #24]
 8000510:	4a3f      	ldr	r2, [pc, #252]	; (8000610 <GPIO_Init+0x114>)
 8000512:	f043 0308 	orr.w	r3, r3, #8
 8000516:	6193      	str	r3, [r2, #24]

	//enable port C
	RCC->APB2ENR |= RCC_APB2ENR_IOPCEN;
 8000518:	4b3d      	ldr	r3, [pc, #244]	; (8000610 <GPIO_Init+0x114>)
 800051a:	699b      	ldr	r3, [r3, #24]
 800051c:	4a3c      	ldr	r2, [pc, #240]	; (8000610 <GPIO_Init+0x114>)
 800051e:	f043 0310 	orr.w	r3, r3, #16
 8000522:	6193      	str	r3, [r2, #24]

	//PC13 as out
	GPIOC->CRH &= ~GPIO_CRH_MODE13;				//clear MODE_CRH13
 8000524:	4b3b      	ldr	r3, [pc, #236]	; (8000614 <GPIO_Init+0x118>)
 8000526:	685b      	ldr	r3, [r3, #4]
 8000528:	4a3a      	ldr	r2, [pc, #232]	; (8000614 <GPIO_Init+0x118>)
 800052a:	f423 1340 	bic.w	r3, r3, #3145728	; 0x300000
 800052e:	6053      	str	r3, [r2, #4]
	GPIOC->CRH &= ~GPIO_CRH_CNF13;				//clear CNF_CRH13
 8000530:	4b38      	ldr	r3, [pc, #224]	; (8000614 <GPIO_Init+0x118>)
 8000532:	685b      	ldr	r3, [r3, #4]
 8000534:	4a37      	ldr	r2, [pc, #220]	; (8000614 <GPIO_Init+0x118>)
 8000536:	f423 0340 	bic.w	r3, r3, #12582912	; 0xc00000
 800053a:	6053      	str	r3, [r2, #4]
	GPIOC->CRH |= (0x01<<GPIO_CRH_MODE13_Pos);	//out mode 10 MHz
 800053c:	4b35      	ldr	r3, [pc, #212]	; (8000614 <GPIO_Init+0x118>)
 800053e:	685b      	ldr	r3, [r3, #4]
 8000540:	4a34      	ldr	r2, [pc, #208]	; (8000614 <GPIO_Init+0x118>)
 8000542:	f443 1380 	orr.w	r3, r3, #1048576	; 0x100000
 8000546:	6053      	str	r3, [r2, #4]
	GPIOC->CRH |= (0x00<<GPIO_CRH_CNF13_Pos);	//push-pull
 8000548:	4b32      	ldr	r3, [pc, #200]	; (8000614 <GPIO_Init+0x118>)
 800054a:	4a32      	ldr	r2, [pc, #200]	; (8000614 <GPIO_Init+0x118>)
 800054c:	685b      	ldr	r3, [r3, #4]
 800054e:	6053      	str	r3, [r2, #4]
	GPIOC->BSRR = GPIO_BSRR_BS13;				//pull-up
 8000550:	4b30      	ldr	r3, [pc, #192]	; (8000614 <GPIO_Init+0x118>)
 8000552:	f44f 5200 	mov.w	r2, #8192	; 0x2000
 8000556:	611a      	str	r2, [r3, #16]

	//PC14 as input
	GPIOC->CRH &= ~GPIO_CRH_MODE14;				//clear MODE_CRH14 (input mode)
 8000558:	4b2e      	ldr	r3, [pc, #184]	; (8000614 <GPIO_Init+0x118>)
 800055a:	685b      	ldr	r3, [r3, #4]
 800055c:	4a2d      	ldr	r2, [pc, #180]	; (8000614 <GPIO_Init+0x118>)
 800055e:	f023 7340 	bic.w	r3, r3, #50331648	; 0x3000000
 8000562:	6053      	str	r3, [r2, #4]
	GPIOC->CRH &= ~GPIO_CRH_CNF14;				//clear CNF_CRH14
 8000564:	4b2b      	ldr	r3, [pc, #172]	; (8000614 <GPIO_Init+0x118>)
 8000566:	685b      	ldr	r3, [r3, #4]
 8000568:	4a2a      	ldr	r2, [pc, #168]	; (8000614 <GPIO_Init+0x118>)
 800056a:	f023 6340 	bic.w	r3, r3, #201326592	; 0xc000000
 800056e:	6053      	str	r3, [r2, #4]
	GPIOC->CRH |= (GPIO_CRH_CNF14_1);			//push-pull
 8000570:	4b28      	ldr	r3, [pc, #160]	; (8000614 <GPIO_Init+0x118>)
 8000572:	685b      	ldr	r3, [r3, #4]
 8000574:	4a27      	ldr	r2, [pc, #156]	; (8000614 <GPIO_Init+0x118>)
 8000576:	f043 6300 	orr.w	r3, r3, #134217728	; 0x8000000
 800057a:	6053      	str	r3, [r2, #4]
	GPIOC->BSRR = GPIO_BSRR_BS14;				//pull to Vcc
 800057c:	4b25      	ldr	r3, [pc, #148]	; (8000614 <GPIO_Init+0x118>)
 800057e:	f44f 4280 	mov.w	r2, #16384	; 0x4000
 8000582:	611a      	str	r2, [r3, #16]

	//PA3 to analog input
	GPIOC->CRL |=(0x00<GPIO_CRL_MODE3_Pos);		//PA3 is input
 8000584:	4b23      	ldr	r3, [pc, #140]	; (8000614 <GPIO_Init+0x118>)
 8000586:	681b      	ldr	r3, [r3, #0]
 8000588:	4a22      	ldr	r2, [pc, #136]	; (8000614 <GPIO_Init+0x118>)
 800058a:	f043 0301 	orr.w	r3, r3, #1
 800058e:	6013      	str	r3, [r2, #0]
	GPIOC->CRL |=(0x00<GPIO_CRL_CNF3_Pos);		//PA3 is analog
 8000590:	4b20      	ldr	r3, [pc, #128]	; (8000614 <GPIO_Init+0x118>)
 8000592:	681b      	ldr	r3, [r3, #0]
 8000594:	4a1f      	ldr	r2, [pc, #124]	; (8000614 <GPIO_Init+0x118>)
 8000596:	f043 0301 	orr.w	r3, r3, #1
 800059a:	6013      	str	r3, [r2, #0]

	//enable alternative func
	RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;
 800059c:	4b1c      	ldr	r3, [pc, #112]	; (8000610 <GPIO_Init+0x114>)
 800059e:	699b      	ldr	r3, [r3, #24]
 80005a0:	4a1b      	ldr	r2, [pc, #108]	; (8000610 <GPIO_Init+0x114>)
 80005a2:	f043 0301 	orr.w	r3, r3, #1
 80005a6:	6193      	str	r3, [r2, #24]

	//PA6 and PA7 as PWM out TIM3
	GPIOA->CRL &= ~GPIO_CRL_MODE6; 				//clear MODE_CRL6
 80005a8:	4b1b      	ldr	r3, [pc, #108]	; (8000618 <GPIO_Init+0x11c>)
 80005aa:	681b      	ldr	r3, [r3, #0]
 80005ac:	4a1a      	ldr	r2, [pc, #104]	; (8000618 <GPIO_Init+0x11c>)
 80005ae:	f023 7340 	bic.w	r3, r3, #50331648	; 0x3000000
 80005b2:	6013      	str	r3, [r2, #0]
	GPIOA->CRL &= ~GPIO_CRL_CNF6; 				//clear CNF_CRL6
 80005b4:	4b18      	ldr	r3, [pc, #96]	; (8000618 <GPIO_Init+0x11c>)
 80005b6:	681b      	ldr	r3, [r3, #0]
 80005b8:	4a17      	ldr	r2, [pc, #92]	; (8000618 <GPIO_Init+0x11c>)
 80005ba:	f023 6340 	bic.w	r3, r3, #201326592	; 0xc000000
 80005be:	6013      	str	r3, [r2, #0]
	GPIOA->CRL |= (0x2<<GPIO_CRL_CNF6_Pos); 	//set alt func and push-pull for PA6
 80005c0:	4b15      	ldr	r3, [pc, #84]	; (8000618 <GPIO_Init+0x11c>)
 80005c2:	681b      	ldr	r3, [r3, #0]
 80005c4:	4a14      	ldr	r2, [pc, #80]	; (8000618 <GPIO_Init+0x11c>)
 80005c6:	f043 6300 	orr.w	r3, r3, #134217728	; 0x8000000
 80005ca:	6013      	str	r3, [r2, #0]
	GPIOA->CRL |= (0x3<<GPIO_CRL_MODE6_Pos); 	//set speed 50 MHz for PA6
 80005cc:	4b12      	ldr	r3, [pc, #72]	; (8000618 <GPIO_Init+0x11c>)
 80005ce:	681b      	ldr	r3, [r3, #0]
 80005d0:	4a11      	ldr	r2, [pc, #68]	; (8000618 <GPIO_Init+0x11c>)
 80005d2:	f043 7340 	orr.w	r3, r3, #50331648	; 0x3000000
 80005d6:	6013      	str	r3, [r2, #0]

	GPIOA->CRL &= ~GPIO_CRL_MODE7; 				//clear MODE_CRL7
 80005d8:	4b0f      	ldr	r3, [pc, #60]	; (8000618 <GPIO_Init+0x11c>)
 80005da:	681b      	ldr	r3, [r3, #0]
 80005dc:	4a0e      	ldr	r2, [pc, #56]	; (8000618 <GPIO_Init+0x11c>)
 80005de:	f023 5340 	bic.w	r3, r3, #805306368	; 0x30000000
 80005e2:	6013      	str	r3, [r2, #0]
	GPIOA->CRL &= ~GPIO_CRL_CNF7; 				//clear CNF_CRL7
 80005e4:	4b0c      	ldr	r3, [pc, #48]	; (8000618 <GPIO_Init+0x11c>)
 80005e6:	681b      	ldr	r3, [r3, #0]
 80005e8:	4a0b      	ldr	r2, [pc, #44]	; (8000618 <GPIO_Init+0x11c>)
 80005ea:	f023 4340 	bic.w	r3, r3, #3221225472	; 0xc0000000
 80005ee:	6013      	str	r3, [r2, #0]
	GPIOA->CRL |= (GPIO_CRL_CNF7_1); 	//set alt func and push-pull for PA7
 80005f0:	4b09      	ldr	r3, [pc, #36]	; (8000618 <GPIO_Init+0x11c>)
 80005f2:	681b      	ldr	r3, [r3, #0]
 80005f4:	4a08      	ldr	r2, [pc, #32]	; (8000618 <GPIO_Init+0x11c>)
 80005f6:	f043 4300 	orr.w	r3, r3, #2147483648	; 0x80000000
 80005fa:	6013      	str	r3, [r2, #0]
	GPIOA->CRL |= (GPIO_CRL_MODE7_1 | GPIO_CRL_MODE7_0); 	//set speed 50 MHz for PA7
 80005fc:	4b06      	ldr	r3, [pc, #24]	; (8000618 <GPIO_Init+0x11c>)
 80005fe:	681b      	ldr	r3, [r3, #0]
 8000600:	4a05      	ldr	r2, [pc, #20]	; (8000618 <GPIO_Init+0x11c>)
 8000602:	f043 5340 	orr.w	r3, r3, #805306368	; 0x30000000
 8000606:	6013      	str	r3, [r2, #0]

	/* GPIO Ports Clock Enable */
	 // __HAL_RCC_GPIOD_CLK_ENABLE();
	 // __HAL_RCC_GPIOB_CLK_ENABLE();

}
 8000608:	bf00      	nop
 800060a:	46bd      	mov	sp, r7
 800060c:	bc80      	pop	{r7}
 800060e:	4770      	bx	lr
 8000610:	40021000 	.word	0x40021000
 8000614:	40011000 	.word	0x40011000
 8000618:	40010800 	.word	0x40010800

0800061c <ADC_Init>:
/**
  * @brief ADC Initialization Function
  * @param None
  * @retval None
  */
static void ADC_Init(void){
 800061c:	b480      	push	{r7}
 800061e:	af00      	add	r7, sp, #0

	RCC->APB2ENR |= RCC_APB2ENR_ADC1EN;		//enable ADC1 clock
 8000620:	4b28      	ldr	r3, [pc, #160]	; (80006c4 <ADC_Init+0xa8>)
 8000622:	699b      	ldr	r3, [r3, #24]
 8000624:	4a27      	ldr	r2, [pc, #156]	; (80006c4 <ADC_Init+0xa8>)
 8000626:	f443 7300 	orr.w	r3, r3, #512	; 0x200
 800062a:	6193      	str	r3, [r2, #24]

	ADC1->CR1 &= ~(ADC_CR1_JEOCIE);			//EOC interrupt disable
 800062c:	4b26      	ldr	r3, [pc, #152]	; (80006c8 <ADC_Init+0xac>)
 800062e:	685b      	ldr	r3, [r3, #4]
 8000630:	4a25      	ldr	r2, [pc, #148]	; (80006c8 <ADC_Init+0xac>)
 8000632:	f023 0380 	bic.w	r3, r3, #128	; 0x80
 8000636:	6053      	str	r3, [r2, #4]
	ADC1->CR1 &= ~(ADC_CR1_AWDIE);			//analog watchdog interrupt disable
 8000638:	4b23      	ldr	r3, [pc, #140]	; (80006c8 <ADC_Init+0xac>)
 800063a:	685b      	ldr	r3, [r3, #4]
 800063c:	4a22      	ldr	r2, [pc, #136]	; (80006c8 <ADC_Init+0xac>)
 800063e:	f023 0340 	bic.w	r3, r3, #64	; 0x40
 8000642:	6053      	str	r3, [r2, #4]
	ADC1->CR1 &= ~(ADC_CR1_JEOSIE);			//injected channels interrupt disable
 8000644:	4b20      	ldr	r3, [pc, #128]	; (80006c8 <ADC_Init+0xac>)
 8000646:	685b      	ldr	r3, [r3, #4]
 8000648:	4a1f      	ldr	r2, [pc, #124]	; (80006c8 <ADC_Init+0xac>)
 800064a:	f023 0380 	bic.w	r3, r3, #128	; 0x80
 800064e:	6053      	str	r3, [r2, #4]
	//ADC1->CR1 |= ADC_CR1_SCAN;			//enable scan mode
	ADC1->CR1 |= (0b0110 << ADC_CR1_DUALMOD_Pos);	//regular channel only
 8000650:	4b1d      	ldr	r3, [pc, #116]	; (80006c8 <ADC_Init+0xac>)
 8000652:	685b      	ldr	r3, [r3, #4]
 8000654:	4a1c      	ldr	r2, [pc, #112]	; (80006c8 <ADC_Init+0xac>)
 8000656:	f443 23c0 	orr.w	r3, r3, #393216	; 0x60000
 800065a:	6053      	str	r3, [r2, #4]

	ADC1->SMPR2 |= (ADC_SMPR2_SMP3_0 | ADC_SMPR2_SMP3_1 | ADC_SMPR2_SMP3_2);	//set 239.5 cycles rate for ch3 adc (pa3)
 800065c:	4b1a      	ldr	r3, [pc, #104]	; (80006c8 <ADC_Init+0xac>)
 800065e:	691b      	ldr	r3, [r3, #16]
 8000660:	4a19      	ldr	r2, [pc, #100]	; (80006c8 <ADC_Init+0xac>)
 8000662:	f443 6360 	orr.w	r3, r3, #3584	; 0xe00
 8000666:	6113      	str	r3, [r2, #16]
	ADC1->SQR1 |= (0b000 << ADC_SQR1_L_Pos); 		//quantity adc channels to convert (1)
 8000668:	4b17      	ldr	r3, [pc, #92]	; (80006c8 <ADC_Init+0xac>)
 800066a:	4a17      	ldr	r2, [pc, #92]	; (80006c8 <ADC_Init+0xac>)
 800066c:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 800066e:	62d3      	str	r3, [r2, #44]	; 0x2c
	ADC1->SQR3 |= (0b00011 << ADC_SQR3_SQ1_Pos);		//first conversion ch3
 8000670:	4b15      	ldr	r3, [pc, #84]	; (80006c8 <ADC_Init+0xac>)
 8000672:	6b5b      	ldr	r3, [r3, #52]	; 0x34
 8000674:	4a14      	ldr	r2, [pc, #80]	; (80006c8 <ADC_Init+0xac>)
 8000676:	f043 0303 	orr.w	r3, r3, #3
 800067a:	6353      	str	r3, [r2, #52]	; 0x34
	//ADC1->SQR3 |= (ADC_SQR3_SQ1_0 | ADC_SQR3_SQ1_1);

	ADC1->CR2 |= ADC_CR2_EXTSEL;	//start conversion by SWSTART bit (program start)
 800067c:	4b12      	ldr	r3, [pc, #72]	; (80006c8 <ADC_Init+0xac>)
 800067e:	689b      	ldr	r3, [r3, #8]
 8000680:	4a11      	ldr	r2, [pc, #68]	; (80006c8 <ADC_Init+0xac>)
 8000682:	f443 2360 	orr.w	r3, r3, #917504	; 0xe0000
 8000686:	6093      	str	r3, [r2, #8]
	ADC1->CR2 |= ADC_CR2_EXTTRIG;	//External trigger conversion mode for regular channels
 8000688:	4b0f      	ldr	r3, [pc, #60]	; (80006c8 <ADC_Init+0xac>)
 800068a:	689b      	ldr	r3, [r3, #8]
 800068c:	4a0e      	ldr	r2, [pc, #56]	; (80006c8 <ADC_Init+0xac>)
 800068e:	f443 1380 	orr.w	r3, r3, #1048576	; 0x100000
 8000692:	6093      	str	r3, [r2, #8]
	ADC1->CR2 |= ADC_CR2_ADON;		//AD converter ON/OFF
 8000694:	4b0c      	ldr	r3, [pc, #48]	; (80006c8 <ADC_Init+0xac>)
 8000696:	689b      	ldr	r3, [r3, #8]
 8000698:	4a0b      	ldr	r2, [pc, #44]	; (80006c8 <ADC_Init+0xac>)
 800069a:	f043 0301 	orr.w	r3, r3, #1
 800069e:	6093      	str	r3, [r2, #8]
	ADC1->CR2 |= ADC_CR2_CAL;		//start adc calibration
 80006a0:	4b09      	ldr	r3, [pc, #36]	; (80006c8 <ADC_Init+0xac>)
 80006a2:	689b      	ldr	r3, [r3, #8]
 80006a4:	4a08      	ldr	r2, [pc, #32]	; (80006c8 <ADC_Init+0xac>)
 80006a6:	f043 0304 	orr.w	r3, r3, #4
 80006aa:	6093      	str	r3, [r2, #8]
	while (!(ADC1->CR2 & ADC_CR2_CAL)){} //wait end of calibration
 80006ac:	bf00      	nop
 80006ae:	4b06      	ldr	r3, [pc, #24]	; (80006c8 <ADC_Init+0xac>)
 80006b0:	689b      	ldr	r3, [r3, #8]
 80006b2:	f003 0304 	and.w	r3, r3, #4
 80006b6:	2b00      	cmp	r3, #0
 80006b8:	d0f9      	beq.n	80006ae <ADC_Init+0x92>

	//ADC1->CR2 |= ADC_CR2_SWSTART;	//start conversion

}
 80006ba:	bf00      	nop
 80006bc:	bf00      	nop
 80006be:	46bd      	mov	sp, r7
 80006c0:	bc80      	pop	{r7}
 80006c2:	4770      	bx	lr
 80006c4:	40021000 	.word	0x40021000
 80006c8:	40012400 	.word	0x40012400

080006cc <Error_Handler>:
/**
  * @brief  This function is executed in case of error occurrence.
  * @retval None
  */
void Error_Handler(void)
{
 80006cc:	b480      	push	{r7}
 80006ce:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN Error_Handler_Debug */
  /* USER CODE END Error_Handler_Debug */
}
 80006d0:	bf00      	nop
 80006d2:	46bd      	mov	sp, r7
 80006d4:	bc80      	pop	{r7}
 80006d6:	4770      	bx	lr

080006d8 <SSD1306_Init>:





uint8_t SSD1306_Init(void) {
 80006d8:	b580      	push	{r7, lr}
 80006da:	b082      	sub	sp, #8
 80006dc:	af00      	add	r7, sp, #0

	/* Init I2C */
	ssd1306_I2C_Init();
 80006de:	f000 fa27 	bl	8000b30 <ssd1306_I2C_Init>
	
	/* Check if LCD connected to I2C */
	if (HAL_I2C_IsDeviceReady(&hi2c1, SSD1306_I2C_ADDR, 1, 20000) != HAL_OK) {
 80006e2:	f644 6320 	movw	r3, #20000	; 0x4e20
 80006e6:	2201      	movs	r2, #1
 80006e8:	2178      	movs	r1, #120	; 0x78
 80006ea:	485b      	ldr	r0, [pc, #364]	; (8000858 <SSD1306_Init+0x180>)
 80006ec:	f001 f89c 	bl	8001828 <HAL_I2C_IsDeviceReady>
 80006f0:	4603      	mov	r3, r0
 80006f2:	2b00      	cmp	r3, #0
 80006f4:	d001      	beq.n	80006fa <SSD1306_Init+0x22>
		/* Return false */
		return 0;
 80006f6:	2300      	movs	r3, #0
 80006f8:	e0a9      	b.n	800084e <SSD1306_Init+0x176>
	}
	
	/* A little delay */
	uint32_t p = 2500;
 80006fa:	f640 13c4 	movw	r3, #2500	; 0x9c4
 80006fe:	607b      	str	r3, [r7, #4]
	while(p>0)
 8000700:	e002      	b.n	8000708 <SSD1306_Init+0x30>
		p--;
 8000702:	687b      	ldr	r3, [r7, #4]
 8000704:	3b01      	subs	r3, #1
 8000706:	607b      	str	r3, [r7, #4]
	while(p>0)
 8000708:	687b      	ldr	r3, [r7, #4]
 800070a:	2b00      	cmp	r3, #0
 800070c:	d1f9      	bne.n	8000702 <SSD1306_Init+0x2a>
	
	/* Init LCD */
	SSD1306_WRITECOMMAND(0xAE); //display off
 800070e:	22ae      	movs	r2, #174	; 0xae
 8000710:	2100      	movs	r1, #0
 8000712:	2078      	movs	r0, #120	; 0x78
 8000714:	f000 fa86 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0x20); //Set Memory Addressing Mode   
 8000718:	2220      	movs	r2, #32
 800071a:	2100      	movs	r1, #0
 800071c:	2078      	movs	r0, #120	; 0x78
 800071e:	f000 fa81 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0x10); //00,Horizontal Addressing Mode;01,Vertical Addressing Mode;10,Page Addressing Mode (RESET);11,Invalid
 8000722:	2210      	movs	r2, #16
 8000724:	2100      	movs	r1, #0
 8000726:	2078      	movs	r0, #120	; 0x78
 8000728:	f000 fa7c 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0xB0); //Set Page Start Address for Page Addressing Mode,0-7
 800072c:	22b0      	movs	r2, #176	; 0xb0
 800072e:	2100      	movs	r1, #0
 8000730:	2078      	movs	r0, #120	; 0x78
 8000732:	f000 fa77 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0xC8); //Set COM Output Scan Direction
 8000736:	22c8      	movs	r2, #200	; 0xc8
 8000738:	2100      	movs	r1, #0
 800073a:	2078      	movs	r0, #120	; 0x78
 800073c:	f000 fa72 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0x00); //---set low column address
 8000740:	2200      	movs	r2, #0
 8000742:	2100      	movs	r1, #0
 8000744:	2078      	movs	r0, #120	; 0x78
 8000746:	f000 fa6d 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0x10); //---set high column address
 800074a:	2210      	movs	r2, #16
 800074c:	2100      	movs	r1, #0
 800074e:	2078      	movs	r0, #120	; 0x78
 8000750:	f000 fa68 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0x40); //--set start line address
 8000754:	2240      	movs	r2, #64	; 0x40
 8000756:	2100      	movs	r1, #0
 8000758:	2078      	movs	r0, #120	; 0x78
 800075a:	f000 fa63 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0x81); //--set contrast control register
 800075e:	2281      	movs	r2, #129	; 0x81
 8000760:	2100      	movs	r1, #0
 8000762:	2078      	movs	r0, #120	; 0x78
 8000764:	f000 fa5e 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0xFF);
 8000768:	22ff      	movs	r2, #255	; 0xff
 800076a:	2100      	movs	r1, #0
 800076c:	2078      	movs	r0, #120	; 0x78
 800076e:	f000 fa59 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0xA1); //--set segment re-map 0 to 127
 8000772:	22a1      	movs	r2, #161	; 0xa1
 8000774:	2100      	movs	r1, #0
 8000776:	2078      	movs	r0, #120	; 0x78
 8000778:	f000 fa54 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0xA6); //--set normal display
 800077c:	22a6      	movs	r2, #166	; 0xa6
 800077e:	2100      	movs	r1, #0
 8000780:	2078      	movs	r0, #120	; 0x78
 8000782:	f000 fa4f 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0xA8); //--set multiplex ratio(1 to 64)
 8000786:	22a8      	movs	r2, #168	; 0xa8
 8000788:	2100      	movs	r1, #0
 800078a:	2078      	movs	r0, #120	; 0x78
 800078c:	f000 fa4a 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0x3F); //
 8000790:	223f      	movs	r2, #63	; 0x3f
 8000792:	2100      	movs	r1, #0
 8000794:	2078      	movs	r0, #120	; 0x78
 8000796:	f000 fa45 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0xA4); //0xa4,Output follows RAM content;0xa5,Output ignores RAM content
 800079a:	22a4      	movs	r2, #164	; 0xa4
 800079c:	2100      	movs	r1, #0
 800079e:	2078      	movs	r0, #120	; 0x78
 80007a0:	f000 fa40 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0xD3); //-set display offset
 80007a4:	22d3      	movs	r2, #211	; 0xd3
 80007a6:	2100      	movs	r1, #0
 80007a8:	2078      	movs	r0, #120	; 0x78
 80007aa:	f000 fa3b 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0x00); //-not offset
 80007ae:	2200      	movs	r2, #0
 80007b0:	2100      	movs	r1, #0
 80007b2:	2078      	movs	r0, #120	; 0x78
 80007b4:	f000 fa36 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0xD5); //--set display clock divide ratio/oscillator frequency
 80007b8:	22d5      	movs	r2, #213	; 0xd5
 80007ba:	2100      	movs	r1, #0
 80007bc:	2078      	movs	r0, #120	; 0x78
 80007be:	f000 fa31 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0xF0); //--set divide ratio
 80007c2:	22f0      	movs	r2, #240	; 0xf0
 80007c4:	2100      	movs	r1, #0
 80007c6:	2078      	movs	r0, #120	; 0x78
 80007c8:	f000 fa2c 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0xD9); //--set pre-charge period
 80007cc:	22d9      	movs	r2, #217	; 0xd9
 80007ce:	2100      	movs	r1, #0
 80007d0:	2078      	movs	r0, #120	; 0x78
 80007d2:	f000 fa27 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0x22); //
 80007d6:	2222      	movs	r2, #34	; 0x22
 80007d8:	2100      	movs	r1, #0
 80007da:	2078      	movs	r0, #120	; 0x78
 80007dc:	f000 fa22 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0xDA); //--set com pins hardware configuration
 80007e0:	22da      	movs	r2, #218	; 0xda
 80007e2:	2100      	movs	r1, #0
 80007e4:	2078      	movs	r0, #120	; 0x78
 80007e6:	f000 fa1d 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0x12);
 80007ea:	2212      	movs	r2, #18
 80007ec:	2100      	movs	r1, #0
 80007ee:	2078      	movs	r0, #120	; 0x78
 80007f0:	f000 fa18 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0xDB); //--set vcomh
 80007f4:	22db      	movs	r2, #219	; 0xdb
 80007f6:	2100      	movs	r1, #0
 80007f8:	2078      	movs	r0, #120	; 0x78
 80007fa:	f000 fa13 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0x20); //0x20,0.77xVcc
 80007fe:	2220      	movs	r2, #32
 8000800:	2100      	movs	r1, #0
 8000802:	2078      	movs	r0, #120	; 0x78
 8000804:	f000 fa0e 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0x8D); //--set DC-DC enable
 8000808:	228d      	movs	r2, #141	; 0x8d
 800080a:	2100      	movs	r1, #0
 800080c:	2078      	movs	r0, #120	; 0x78
 800080e:	f000 fa09 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0x14); //
 8000812:	2214      	movs	r2, #20
 8000814:	2100      	movs	r1, #0
 8000816:	2078      	movs	r0, #120	; 0x78
 8000818:	f000 fa04 	bl	8000c24 <ssd1306_I2C_Write>
	SSD1306_WRITECOMMAND(0xAF); //--turn on SSD1306 panel
 800081c:	22af      	movs	r2, #175	; 0xaf
 800081e:	2100      	movs	r1, #0
 8000820:	2078      	movs	r0, #120	; 0x78
 8000822:	f000 f9ff 	bl	8000c24 <ssd1306_I2C_Write>
	

	SSD1306_WRITECOMMAND(SSD1306_DEACTIVATE_SCROLL);
 8000826:	222e      	movs	r2, #46	; 0x2e
 8000828:	2100      	movs	r1, #0
 800082a:	2078      	movs	r0, #120	; 0x78
 800082c:	f000 f9fa 	bl	8000c24 <ssd1306_I2C_Write>

	/* Clear screen */
	SSD1306_Fill(SSD1306_COLOR_BLACK);
 8000830:	2000      	movs	r0, #0
 8000832:	f000 f843 	bl	80008bc <SSD1306_Fill>
	
	/* Update screen */
	SSD1306_UpdateScreen();
 8000836:	f000 f813 	bl	8000860 <SSD1306_UpdateScreen>
	
	/* Set default values */
	SSD1306.CurrentX = 0;
 800083a:	4b08      	ldr	r3, [pc, #32]	; (800085c <SSD1306_Init+0x184>)
 800083c:	2200      	movs	r2, #0
 800083e:	801a      	strh	r2, [r3, #0]
	SSD1306.CurrentY = 0;
 8000840:	4b06      	ldr	r3, [pc, #24]	; (800085c <SSD1306_Init+0x184>)
 8000842:	2200      	movs	r2, #0
 8000844:	805a      	strh	r2, [r3, #2]
	
	/* Initialized OK */
	SSD1306.Initialized = 1;
 8000846:	4b05      	ldr	r3, [pc, #20]	; (800085c <SSD1306_Init+0x184>)
 8000848:	2201      	movs	r2, #1
 800084a:	715a      	strb	r2, [r3, #5]
	
	/* Return OK */
	return 1;
 800084c:	2301      	movs	r3, #1
}
 800084e:	4618      	mov	r0, r3
 8000850:	3708      	adds	r7, #8
 8000852:	46bd      	mov	sp, r7
 8000854:	bd80      	pop	{r7, pc}
 8000856:	bf00      	nop
 8000858:	20000038 	.word	0x20000038
 800085c:	20000494 	.word	0x20000494

08000860 <SSD1306_UpdateScreen>:

void SSD1306_UpdateScreen(void) {
 8000860:	b580      	push	{r7, lr}
 8000862:	b082      	sub	sp, #8
 8000864:	af00      	add	r7, sp, #0
	uint8_t m;
	
	for (m = 0; m < 8; m++) {
 8000866:	2300      	movs	r3, #0
 8000868:	71fb      	strb	r3, [r7, #7]
 800086a:	e01d      	b.n	80008a8 <SSD1306_UpdateScreen+0x48>
		SSD1306_WRITECOMMAND(0xB0 + m);
 800086c:	79fb      	ldrb	r3, [r7, #7]
 800086e:	3b50      	subs	r3, #80	; 0x50
 8000870:	b2db      	uxtb	r3, r3
 8000872:	461a      	mov	r2, r3
 8000874:	2100      	movs	r1, #0
 8000876:	2078      	movs	r0, #120	; 0x78
 8000878:	f000 f9d4 	bl	8000c24 <ssd1306_I2C_Write>
		SSD1306_WRITECOMMAND(0x00);
 800087c:	2200      	movs	r2, #0
 800087e:	2100      	movs	r1, #0
 8000880:	2078      	movs	r0, #120	; 0x78
 8000882:	f000 f9cf 	bl	8000c24 <ssd1306_I2C_Write>
		SSD1306_WRITECOMMAND(0x10);
 8000886:	2210      	movs	r2, #16
 8000888:	2100      	movs	r1, #0
 800088a:	2078      	movs	r0, #120	; 0x78
 800088c:	f000 f9ca 	bl	8000c24 <ssd1306_I2C_Write>
		
		/* Write multi data */
		ssd1306_I2C_WriteMulti(SSD1306_I2C_ADDR, 0x40, &SSD1306_Buffer[SSD1306_WIDTH * m], SSD1306_WIDTH);
 8000890:	79fb      	ldrb	r3, [r7, #7]
 8000892:	01db      	lsls	r3, r3, #7
 8000894:	4a08      	ldr	r2, [pc, #32]	; (80008b8 <SSD1306_UpdateScreen+0x58>)
 8000896:	441a      	add	r2, r3
 8000898:	2380      	movs	r3, #128	; 0x80
 800089a:	2140      	movs	r1, #64	; 0x40
 800089c:	2078      	movs	r0, #120	; 0x78
 800089e:	f000 f95b 	bl	8000b58 <ssd1306_I2C_WriteMulti>
	for (m = 0; m < 8; m++) {
 80008a2:	79fb      	ldrb	r3, [r7, #7]
 80008a4:	3301      	adds	r3, #1
 80008a6:	71fb      	strb	r3, [r7, #7]
 80008a8:	79fb      	ldrb	r3, [r7, #7]
 80008aa:	2b07      	cmp	r3, #7
 80008ac:	d9de      	bls.n	800086c <SSD1306_UpdateScreen+0xc>
	}
}
 80008ae:	bf00      	nop
 80008b0:	bf00      	nop
 80008b2:	3708      	adds	r7, #8
 80008b4:	46bd      	mov	sp, r7
 80008b6:	bd80      	pop	{r7, pc}
 80008b8:	20000094 	.word	0x20000094

080008bc <SSD1306_Fill>:
	for (i = 0; i < sizeof(SSD1306_Buffer); i++) {
		SSD1306_Buffer[i] = ~SSD1306_Buffer[i];
	}
}

void SSD1306_Fill(SSD1306_COLOR_t color) {
 80008bc:	b580      	push	{r7, lr}
 80008be:	b082      	sub	sp, #8
 80008c0:	af00      	add	r7, sp, #0
 80008c2:	4603      	mov	r3, r0
 80008c4:	71fb      	strb	r3, [r7, #7]
	/* Set memory */
	memset(SSD1306_Buffer, (color == SSD1306_COLOR_BLACK) ? 0x00 : 0xFF, sizeof(SSD1306_Buffer));
 80008c6:	79fb      	ldrb	r3, [r7, #7]
 80008c8:	2b00      	cmp	r3, #0
 80008ca:	d101      	bne.n	80008d0 <SSD1306_Fill+0x14>
 80008cc:	2300      	movs	r3, #0
 80008ce:	e000      	b.n	80008d2 <SSD1306_Fill+0x16>
 80008d0:	23ff      	movs	r3, #255	; 0xff
 80008d2:	f44f 6280 	mov.w	r2, #1024	; 0x400
 80008d6:	4619      	mov	r1, r3
 80008d8:	4803      	ldr	r0, [pc, #12]	; (80008e8 <SSD1306_Fill+0x2c>)
 80008da:	f001 ff85 	bl	80027e8 <memset>
}
 80008de:	bf00      	nop
 80008e0:	3708      	adds	r7, #8
 80008e2:	46bd      	mov	sp, r7
 80008e4:	bd80      	pop	{r7, pc}
 80008e6:	bf00      	nop
 80008e8:	20000094 	.word	0x20000094

080008ec <SSD1306_DrawPixel>:

void SSD1306_DrawPixel(uint16_t x, uint16_t y, SSD1306_COLOR_t color) {
 80008ec:	b480      	push	{r7}
 80008ee:	b083      	sub	sp, #12
 80008f0:	af00      	add	r7, sp, #0
 80008f2:	4603      	mov	r3, r0
 80008f4:	80fb      	strh	r3, [r7, #6]
 80008f6:	460b      	mov	r3, r1
 80008f8:	80bb      	strh	r3, [r7, #4]
 80008fa:	4613      	mov	r3, r2
 80008fc:	70fb      	strb	r3, [r7, #3]
	if (
 80008fe:	88fb      	ldrh	r3, [r7, #6]
 8000900:	2b7f      	cmp	r3, #127	; 0x7f
 8000902:	d848      	bhi.n	8000996 <SSD1306_DrawPixel+0xaa>
		x >= SSD1306_WIDTH ||
 8000904:	88bb      	ldrh	r3, [r7, #4]
 8000906:	2b3f      	cmp	r3, #63	; 0x3f
 8000908:	d845      	bhi.n	8000996 <SSD1306_DrawPixel+0xaa>
		/* Error */
		return;
	}
	
	/* Check if pixels are inverted */
	if (SSD1306.Inverted) {
 800090a:	4b25      	ldr	r3, [pc, #148]	; (80009a0 <SSD1306_DrawPixel+0xb4>)
 800090c:	791b      	ldrb	r3, [r3, #4]
 800090e:	2b00      	cmp	r3, #0
 8000910:	d006      	beq.n	8000920 <SSD1306_DrawPixel+0x34>
		color = (SSD1306_COLOR_t)!color;
 8000912:	78fb      	ldrb	r3, [r7, #3]
 8000914:	2b00      	cmp	r3, #0
 8000916:	bf0c      	ite	eq
 8000918:	2301      	moveq	r3, #1
 800091a:	2300      	movne	r3, #0
 800091c:	b2db      	uxtb	r3, r3
 800091e:	70fb      	strb	r3, [r7, #3]
	}
	
	/* Set color */
	if (color == SSD1306_COLOR_WHITE) {
 8000920:	78fb      	ldrb	r3, [r7, #3]
 8000922:	2b01      	cmp	r3, #1
 8000924:	d11a      	bne.n	800095c <SSD1306_DrawPixel+0x70>
		SSD1306_Buffer[x + (y / 8) * SSD1306_WIDTH] |= 1 << (y % 8);
 8000926:	88fa      	ldrh	r2, [r7, #6]
 8000928:	88bb      	ldrh	r3, [r7, #4]
 800092a:	08db      	lsrs	r3, r3, #3
 800092c:	b298      	uxth	r0, r3
 800092e:	4603      	mov	r3, r0
 8000930:	01db      	lsls	r3, r3, #7
 8000932:	4413      	add	r3, r2
 8000934:	4a1b      	ldr	r2, [pc, #108]	; (80009a4 <SSD1306_DrawPixel+0xb8>)
 8000936:	5cd3      	ldrb	r3, [r2, r3]
 8000938:	b25a      	sxtb	r2, r3
 800093a:	88bb      	ldrh	r3, [r7, #4]
 800093c:	f003 0307 	and.w	r3, r3, #7
 8000940:	2101      	movs	r1, #1
 8000942:	fa01 f303 	lsl.w	r3, r1, r3
 8000946:	b25b      	sxtb	r3, r3
 8000948:	4313      	orrs	r3, r2
 800094a:	b259      	sxtb	r1, r3
 800094c:	88fa      	ldrh	r2, [r7, #6]
 800094e:	4603      	mov	r3, r0
 8000950:	01db      	lsls	r3, r3, #7
 8000952:	4413      	add	r3, r2
 8000954:	b2c9      	uxtb	r1, r1
 8000956:	4a13      	ldr	r2, [pc, #76]	; (80009a4 <SSD1306_DrawPixel+0xb8>)
 8000958:	54d1      	strb	r1, [r2, r3]
 800095a:	e01d      	b.n	8000998 <SSD1306_DrawPixel+0xac>
	} else {
		SSD1306_Buffer[x + (y / 8) * SSD1306_WIDTH] &= ~(1 << (y % 8));
 800095c:	88fa      	ldrh	r2, [r7, #6]
 800095e:	88bb      	ldrh	r3, [r7, #4]
 8000960:	08db      	lsrs	r3, r3, #3
 8000962:	b298      	uxth	r0, r3
 8000964:	4603      	mov	r3, r0
 8000966:	01db      	lsls	r3, r3, #7
 8000968:	4413      	add	r3, r2
 800096a:	4a0e      	ldr	r2, [pc, #56]	; (80009a4 <SSD1306_DrawPixel+0xb8>)
 800096c:	5cd3      	ldrb	r3, [r2, r3]
 800096e:	b25a      	sxtb	r2, r3
 8000970:	88bb      	ldrh	r3, [r7, #4]
 8000972:	f003 0307 	and.w	r3, r3, #7
 8000976:	2101      	movs	r1, #1
 8000978:	fa01 f303 	lsl.w	r3, r1, r3
 800097c:	b25b      	sxtb	r3, r3
 800097e:	43db      	mvns	r3, r3
 8000980:	b25b      	sxtb	r3, r3
 8000982:	4013      	ands	r3, r2
 8000984:	b259      	sxtb	r1, r3
 8000986:	88fa      	ldrh	r2, [r7, #6]
 8000988:	4603      	mov	r3, r0
 800098a:	01db      	lsls	r3, r3, #7
 800098c:	4413      	add	r3, r2
 800098e:	b2c9      	uxtb	r1, r1
 8000990:	4a04      	ldr	r2, [pc, #16]	; (80009a4 <SSD1306_DrawPixel+0xb8>)
 8000992:	54d1      	strb	r1, [r2, r3]
 8000994:	e000      	b.n	8000998 <SSD1306_DrawPixel+0xac>
		return;
 8000996:	bf00      	nop
	}
}
 8000998:	370c      	adds	r7, #12
 800099a:	46bd      	mov	sp, r7
 800099c:	bc80      	pop	{r7}
 800099e:	4770      	bx	lr
 80009a0:	20000494 	.word	0x20000494
 80009a4:	20000094 	.word	0x20000094

080009a8 <SSD1306_GotoXY>:

void SSD1306_GotoXY(uint16_t x, uint16_t y) {
 80009a8:	b480      	push	{r7}
 80009aa:	b083      	sub	sp, #12
 80009ac:	af00      	add	r7, sp, #0
 80009ae:	4603      	mov	r3, r0
 80009b0:	460a      	mov	r2, r1
 80009b2:	80fb      	strh	r3, [r7, #6]
 80009b4:	4613      	mov	r3, r2
 80009b6:	80bb      	strh	r3, [r7, #4]
	/* Set write pointers */
	SSD1306.CurrentX = x;
 80009b8:	4a05      	ldr	r2, [pc, #20]	; (80009d0 <SSD1306_GotoXY+0x28>)
 80009ba:	88fb      	ldrh	r3, [r7, #6]
 80009bc:	8013      	strh	r3, [r2, #0]
	SSD1306.CurrentY = y;
 80009be:	4a04      	ldr	r2, [pc, #16]	; (80009d0 <SSD1306_GotoXY+0x28>)
 80009c0:	88bb      	ldrh	r3, [r7, #4]
 80009c2:	8053      	strh	r3, [r2, #2]
}
 80009c4:	bf00      	nop
 80009c6:	370c      	adds	r7, #12
 80009c8:	46bd      	mov	sp, r7
 80009ca:	bc80      	pop	{r7}
 80009cc:	4770      	bx	lr
 80009ce:	bf00      	nop
 80009d0:	20000494 	.word	0x20000494

080009d4 <SSD1306_Putc>:

char SSD1306_Putc(char ch, FontDef_t* Font, SSD1306_COLOR_t color) {
 80009d4:	b580      	push	{r7, lr}
 80009d6:	b086      	sub	sp, #24
 80009d8:	af00      	add	r7, sp, #0
 80009da:	4603      	mov	r3, r0
 80009dc:	6039      	str	r1, [r7, #0]
 80009de:	71fb      	strb	r3, [r7, #7]
 80009e0:	4613      	mov	r3, r2
 80009e2:	71bb      	strb	r3, [r7, #6]
	uint32_t i, b, j;
	
	/* Check available space in LCD */
	if (
		SSD1306_WIDTH <= (SSD1306.CurrentX + Font->FontWidth) ||
 80009e4:	4b3a      	ldr	r3, [pc, #232]	; (8000ad0 <SSD1306_Putc+0xfc>)
 80009e6:	881b      	ldrh	r3, [r3, #0]
 80009e8:	461a      	mov	r2, r3
 80009ea:	683b      	ldr	r3, [r7, #0]
 80009ec:	781b      	ldrb	r3, [r3, #0]
 80009ee:	4413      	add	r3, r2
	if (
 80009f0:	2b7f      	cmp	r3, #127	; 0x7f
 80009f2:	dc07      	bgt.n	8000a04 <SSD1306_Putc+0x30>
		SSD1306_HEIGHT <= (SSD1306.CurrentY + Font->FontHeight)
 80009f4:	4b36      	ldr	r3, [pc, #216]	; (8000ad0 <SSD1306_Putc+0xfc>)
 80009f6:	885b      	ldrh	r3, [r3, #2]
 80009f8:	461a      	mov	r2, r3
 80009fa:	683b      	ldr	r3, [r7, #0]
 80009fc:	785b      	ldrb	r3, [r3, #1]
 80009fe:	4413      	add	r3, r2
		SSD1306_WIDTH <= (SSD1306.CurrentX + Font->FontWidth) ||
 8000a00:	2b3f      	cmp	r3, #63	; 0x3f
 8000a02:	dd01      	ble.n	8000a08 <SSD1306_Putc+0x34>
	) {
		/* Error */
		return 0;
 8000a04:	2300      	movs	r3, #0
 8000a06:	e05e      	b.n	8000ac6 <SSD1306_Putc+0xf2>
	}
	
	/* Go through font */
	for (i = 0; i < Font->FontHeight; i++) {
 8000a08:	2300      	movs	r3, #0
 8000a0a:	617b      	str	r3, [r7, #20]
 8000a0c:	e04b      	b.n	8000aa6 <SSD1306_Putc+0xd2>
		b = Font->data[(ch - 32) * Font->FontHeight + i];
 8000a0e:	683b      	ldr	r3, [r7, #0]
 8000a10:	685a      	ldr	r2, [r3, #4]
 8000a12:	79fb      	ldrb	r3, [r7, #7]
 8000a14:	3b20      	subs	r3, #32
 8000a16:	6839      	ldr	r1, [r7, #0]
 8000a18:	7849      	ldrb	r1, [r1, #1]
 8000a1a:	fb01 f303 	mul.w	r3, r1, r3
 8000a1e:	4619      	mov	r1, r3
 8000a20:	697b      	ldr	r3, [r7, #20]
 8000a22:	440b      	add	r3, r1
 8000a24:	005b      	lsls	r3, r3, #1
 8000a26:	4413      	add	r3, r2
 8000a28:	881b      	ldrh	r3, [r3, #0]
 8000a2a:	60fb      	str	r3, [r7, #12]
		for (j = 0; j < Font->FontWidth; j++) {
 8000a2c:	2300      	movs	r3, #0
 8000a2e:	613b      	str	r3, [r7, #16]
 8000a30:	e030      	b.n	8000a94 <SSD1306_Putc+0xc0>
			if ((b << j) & 0x8000) {
 8000a32:	68fa      	ldr	r2, [r7, #12]
 8000a34:	693b      	ldr	r3, [r7, #16]
 8000a36:	fa02 f303 	lsl.w	r3, r2, r3
 8000a3a:	f403 4300 	and.w	r3, r3, #32768	; 0x8000
 8000a3e:	2b00      	cmp	r3, #0
 8000a40:	d010      	beq.n	8000a64 <SSD1306_Putc+0x90>
				SSD1306_DrawPixel(SSD1306.CurrentX + j, (SSD1306.CurrentY + i), (SSD1306_COLOR_t) color);
 8000a42:	4b23      	ldr	r3, [pc, #140]	; (8000ad0 <SSD1306_Putc+0xfc>)
 8000a44:	881a      	ldrh	r2, [r3, #0]
 8000a46:	693b      	ldr	r3, [r7, #16]
 8000a48:	b29b      	uxth	r3, r3
 8000a4a:	4413      	add	r3, r2
 8000a4c:	b298      	uxth	r0, r3
 8000a4e:	4b20      	ldr	r3, [pc, #128]	; (8000ad0 <SSD1306_Putc+0xfc>)
 8000a50:	885a      	ldrh	r2, [r3, #2]
 8000a52:	697b      	ldr	r3, [r7, #20]
 8000a54:	b29b      	uxth	r3, r3
 8000a56:	4413      	add	r3, r2
 8000a58:	b29b      	uxth	r3, r3
 8000a5a:	79ba      	ldrb	r2, [r7, #6]
 8000a5c:	4619      	mov	r1, r3
 8000a5e:	f7ff ff45 	bl	80008ec <SSD1306_DrawPixel>
 8000a62:	e014      	b.n	8000a8e <SSD1306_Putc+0xba>
			} else {
				SSD1306_DrawPixel(SSD1306.CurrentX + j, (SSD1306.CurrentY + i), (SSD1306_COLOR_t)!color);
 8000a64:	4b1a      	ldr	r3, [pc, #104]	; (8000ad0 <SSD1306_Putc+0xfc>)
 8000a66:	881a      	ldrh	r2, [r3, #0]
 8000a68:	693b      	ldr	r3, [r7, #16]
 8000a6a:	b29b      	uxth	r3, r3
 8000a6c:	4413      	add	r3, r2
 8000a6e:	b298      	uxth	r0, r3
 8000a70:	4b17      	ldr	r3, [pc, #92]	; (8000ad0 <SSD1306_Putc+0xfc>)
 8000a72:	885a      	ldrh	r2, [r3, #2]
 8000a74:	697b      	ldr	r3, [r7, #20]
 8000a76:	b29b      	uxth	r3, r3
 8000a78:	4413      	add	r3, r2
 8000a7a:	b299      	uxth	r1, r3
 8000a7c:	79bb      	ldrb	r3, [r7, #6]
 8000a7e:	2b00      	cmp	r3, #0
 8000a80:	bf0c      	ite	eq
 8000a82:	2301      	moveq	r3, #1
 8000a84:	2300      	movne	r3, #0
 8000a86:	b2db      	uxtb	r3, r3
 8000a88:	461a      	mov	r2, r3
 8000a8a:	f7ff ff2f 	bl	80008ec <SSD1306_DrawPixel>
		for (j = 0; j < Font->FontWidth; j++) {
 8000a8e:	693b      	ldr	r3, [r7, #16]
 8000a90:	3301      	adds	r3, #1
 8000a92:	613b      	str	r3, [r7, #16]
 8000a94:	683b      	ldr	r3, [r7, #0]
 8000a96:	781b      	ldrb	r3, [r3, #0]
 8000a98:	461a      	mov	r2, r3
 8000a9a:	693b      	ldr	r3, [r7, #16]
 8000a9c:	4293      	cmp	r3, r2
 8000a9e:	d3c8      	bcc.n	8000a32 <SSD1306_Putc+0x5e>
	for (i = 0; i < Font->FontHeight; i++) {
 8000aa0:	697b      	ldr	r3, [r7, #20]
 8000aa2:	3301      	adds	r3, #1
 8000aa4:	617b      	str	r3, [r7, #20]
 8000aa6:	683b      	ldr	r3, [r7, #0]
 8000aa8:	785b      	ldrb	r3, [r3, #1]
 8000aaa:	461a      	mov	r2, r3
 8000aac:	697b      	ldr	r3, [r7, #20]
 8000aae:	4293      	cmp	r3, r2
 8000ab0:	d3ad      	bcc.n	8000a0e <SSD1306_Putc+0x3a>
			}
		}
	}
	
	/* Increase pointer */
	SSD1306.CurrentX += Font->FontWidth;
 8000ab2:	4b07      	ldr	r3, [pc, #28]	; (8000ad0 <SSD1306_Putc+0xfc>)
 8000ab4:	881a      	ldrh	r2, [r3, #0]
 8000ab6:	683b      	ldr	r3, [r7, #0]
 8000ab8:	781b      	ldrb	r3, [r3, #0]
 8000aba:	b29b      	uxth	r3, r3
 8000abc:	4413      	add	r3, r2
 8000abe:	b29a      	uxth	r2, r3
 8000ac0:	4b03      	ldr	r3, [pc, #12]	; (8000ad0 <SSD1306_Putc+0xfc>)
 8000ac2:	801a      	strh	r2, [r3, #0]
	
	/* Return character written */
	return ch;
 8000ac4:	79fb      	ldrb	r3, [r7, #7]
}
 8000ac6:	4618      	mov	r0, r3
 8000ac8:	3718      	adds	r7, #24
 8000aca:	46bd      	mov	sp, r7
 8000acc:	bd80      	pop	{r7, pc}
 8000ace:	bf00      	nop
 8000ad0:	20000494 	.word	0x20000494

08000ad4 <SSD1306_Puts>:

char SSD1306_Puts(char* str, FontDef_t* Font, SSD1306_COLOR_t color) {
 8000ad4:	b580      	push	{r7, lr}
 8000ad6:	b084      	sub	sp, #16
 8000ad8:	af00      	add	r7, sp, #0
 8000ada:	60f8      	str	r0, [r7, #12]
 8000adc:	60b9      	str	r1, [r7, #8]
 8000ade:	4613      	mov	r3, r2
 8000ae0:	71fb      	strb	r3, [r7, #7]
	/* Write characters */
	while (*str) {
 8000ae2:	e012      	b.n	8000b0a <SSD1306_Puts+0x36>
		/* Write character by character */
		if (SSD1306_Putc(*str, Font, color) != *str) {
 8000ae4:	68fb      	ldr	r3, [r7, #12]
 8000ae6:	781b      	ldrb	r3, [r3, #0]
 8000ae8:	79fa      	ldrb	r2, [r7, #7]
 8000aea:	68b9      	ldr	r1, [r7, #8]
 8000aec:	4618      	mov	r0, r3
 8000aee:	f7ff ff71 	bl	80009d4 <SSD1306_Putc>
 8000af2:	4603      	mov	r3, r0
 8000af4:	461a      	mov	r2, r3
 8000af6:	68fb      	ldr	r3, [r7, #12]
 8000af8:	781b      	ldrb	r3, [r3, #0]
 8000afa:	429a      	cmp	r2, r3
 8000afc:	d002      	beq.n	8000b04 <SSD1306_Puts+0x30>
			/* Return error */
			return *str;
 8000afe:	68fb      	ldr	r3, [r7, #12]
 8000b00:	781b      	ldrb	r3, [r3, #0]
 8000b02:	e008      	b.n	8000b16 <SSD1306_Puts+0x42>
		}
		
		/* Increase string pointer */
		str++;
 8000b04:	68fb      	ldr	r3, [r7, #12]
 8000b06:	3301      	adds	r3, #1
 8000b08:	60fb      	str	r3, [r7, #12]
	while (*str) {
 8000b0a:	68fb      	ldr	r3, [r7, #12]
 8000b0c:	781b      	ldrb	r3, [r3, #0]
 8000b0e:	2b00      	cmp	r3, #0
 8000b10:	d1e8      	bne.n	8000ae4 <SSD1306_Puts+0x10>
	}
	
	/* Everything OK, zero should be returned */
	return *str;
 8000b12:	68fb      	ldr	r3, [r7, #12]
 8000b14:	781b      	ldrb	r3, [r3, #0]
}
 8000b16:	4618      	mov	r0, r3
 8000b18:	3710      	adds	r7, #16
 8000b1a:	46bd      	mov	sp, r7
 8000b1c:	bd80      	pop	{r7, pc}

08000b1e <SSD1306_Clear>:
}
 


void SSD1306_Clear (void)
{
 8000b1e:	b580      	push	{r7, lr}
 8000b20:	af00      	add	r7, sp, #0
	SSD1306_Fill (0);
 8000b22:	2000      	movs	r0, #0
 8000b24:	f7ff feca 	bl	80008bc <SSD1306_Fill>
    SSD1306_UpdateScreen();
 8000b28:	f7ff fe9a 	bl	8000860 <SSD1306_UpdateScreen>
}
 8000b2c:	bf00      	nop
 8000b2e:	bd80      	pop	{r7, pc}

08000b30 <ssd1306_I2C_Init>:
//  _| |_ / /_| |____ 
// |_____|____|\_____|
//
/////////////////////////////////////////////////////////////////////////////////////////////////////////

void ssd1306_I2C_Init() {
 8000b30:	b480      	push	{r7}
 8000b32:	b083      	sub	sp, #12
 8000b34:	af00      	add	r7, sp, #0
	//MX_I2C1_Init();
	uint32_t p = 250000;
 8000b36:	4b07      	ldr	r3, [pc, #28]	; (8000b54 <ssd1306_I2C_Init+0x24>)
 8000b38:	607b      	str	r3, [r7, #4]
	while(p>0)
 8000b3a:	e002      	b.n	8000b42 <ssd1306_I2C_Init+0x12>
		p--;
 8000b3c:	687b      	ldr	r3, [r7, #4]
 8000b3e:	3b01      	subs	r3, #1
 8000b40:	607b      	str	r3, [r7, #4]
	while(p>0)
 8000b42:	687b      	ldr	r3, [r7, #4]
 8000b44:	2b00      	cmp	r3, #0
 8000b46:	d1f9      	bne.n	8000b3c <ssd1306_I2C_Init+0xc>
	//HAL_I2C_DeInit(&hi2c1);
	//p = 250000;
	//while(p>0)
	//	p--;
	//MX_I2C1_Init();
}
 8000b48:	bf00      	nop
 8000b4a:	bf00      	nop
 8000b4c:	370c      	adds	r7, #12
 8000b4e:	46bd      	mov	sp, r7
 8000b50:	bc80      	pop	{r7}
 8000b52:	4770      	bx	lr
 8000b54:	0003d090 	.word	0x0003d090

08000b58 <ssd1306_I2C_WriteMulti>:

void ssd1306_I2C_WriteMulti(uint8_t address, uint8_t reg, uint8_t* data, uint16_t count) {
 8000b58:	b590      	push	{r4, r7, lr}
 8000b5a:	b0c7      	sub	sp, #284	; 0x11c
 8000b5c:	af02      	add	r7, sp, #8
 8000b5e:	4604      	mov	r4, r0
 8000b60:	4608      	mov	r0, r1
 8000b62:	f507 7188 	add.w	r1, r7, #272	; 0x110
 8000b66:	f5a1 7188 	sub.w	r1, r1, #272	; 0x110
 8000b6a:	600a      	str	r2, [r1, #0]
 8000b6c:	4619      	mov	r1, r3
 8000b6e:	f507 7388 	add.w	r3, r7, #272	; 0x110
 8000b72:	f2a3 1309 	subw	r3, r3, #265	; 0x109
 8000b76:	4622      	mov	r2, r4
 8000b78:	701a      	strb	r2, [r3, #0]
 8000b7a:	f507 7388 	add.w	r3, r7, #272	; 0x110
 8000b7e:	f5a3 7385 	sub.w	r3, r3, #266	; 0x10a
 8000b82:	4602      	mov	r2, r0
 8000b84:	701a      	strb	r2, [r3, #0]
 8000b86:	f507 7388 	add.w	r3, r7, #272	; 0x110
 8000b8a:	f5a3 7386 	sub.w	r3, r3, #268	; 0x10c
 8000b8e:	460a      	mov	r2, r1
 8000b90:	801a      	strh	r2, [r3, #0]
uint8_t dt[256];
dt[0] = reg;
 8000b92:	f507 7388 	add.w	r3, r7, #272	; 0x110
 8000b96:	f5a3 7382 	sub.w	r3, r3, #260	; 0x104
 8000b9a:	f507 7288 	add.w	r2, r7, #272	; 0x110
 8000b9e:	f5a2 7285 	sub.w	r2, r2, #266	; 0x10a
 8000ba2:	7812      	ldrb	r2, [r2, #0]
 8000ba4:	701a      	strb	r2, [r3, #0]
uint8_t i;
for(i = 0; i < count; i++)
 8000ba6:	2300      	movs	r3, #0
 8000ba8:	f887 310f 	strb.w	r3, [r7, #271]	; 0x10f
 8000bac:	e015      	b.n	8000bda <ssd1306_I2C_WriteMulti+0x82>
dt[i+1] = data[i];
 8000bae:	f897 310f 	ldrb.w	r3, [r7, #271]	; 0x10f
 8000bb2:	f507 7288 	add.w	r2, r7, #272	; 0x110
 8000bb6:	f5a2 7288 	sub.w	r2, r2, #272	; 0x110
 8000bba:	6812      	ldr	r2, [r2, #0]
 8000bbc:	441a      	add	r2, r3
 8000bbe:	f897 310f 	ldrb.w	r3, [r7, #271]	; 0x10f
 8000bc2:	3301      	adds	r3, #1
 8000bc4:	7811      	ldrb	r1, [r2, #0]
 8000bc6:	f507 7288 	add.w	r2, r7, #272	; 0x110
 8000bca:	f5a2 7282 	sub.w	r2, r2, #260	; 0x104
 8000bce:	54d1      	strb	r1, [r2, r3]
for(i = 0; i < count; i++)
 8000bd0:	f897 310f 	ldrb.w	r3, [r7, #271]	; 0x10f
 8000bd4:	3301      	adds	r3, #1
 8000bd6:	f887 310f 	strb.w	r3, [r7, #271]	; 0x10f
 8000bda:	f897 310f 	ldrb.w	r3, [r7, #271]	; 0x10f
 8000bde:	b29b      	uxth	r3, r3
 8000be0:	f507 7288 	add.w	r2, r7, #272	; 0x110
 8000be4:	f5a2 7286 	sub.w	r2, r2, #268	; 0x10c
 8000be8:	8812      	ldrh	r2, [r2, #0]
 8000bea:	429a      	cmp	r2, r3
 8000bec:	d8df      	bhi.n	8000bae <ssd1306_I2C_WriteMulti+0x56>
HAL_I2C_Master_Transmit(&hi2c1, address, dt, count+1, 10);
 8000bee:	f507 7388 	add.w	r3, r7, #272	; 0x110
 8000bf2:	f2a3 1309 	subw	r3, r3, #265	; 0x109
 8000bf6:	781b      	ldrb	r3, [r3, #0]
 8000bf8:	b299      	uxth	r1, r3
 8000bfa:	f507 7388 	add.w	r3, r7, #272	; 0x110
 8000bfe:	f5a3 7386 	sub.w	r3, r3, #268	; 0x10c
 8000c02:	881b      	ldrh	r3, [r3, #0]
 8000c04:	3301      	adds	r3, #1
 8000c06:	b29b      	uxth	r3, r3
 8000c08:	f107 020c 	add.w	r2, r7, #12
 8000c0c:	200a      	movs	r0, #10
 8000c0e:	9000      	str	r0, [sp, #0]
 8000c10:	4803      	ldr	r0, [pc, #12]	; (8000c20 <ssd1306_I2C_WriteMulti+0xc8>)
 8000c12:	f000 fd0b 	bl	800162c <HAL_I2C_Master_Transmit>
}
 8000c16:	bf00      	nop
 8000c18:	f507 778a 	add.w	r7, r7, #276	; 0x114
 8000c1c:	46bd      	mov	sp, r7
 8000c1e:	bd90      	pop	{r4, r7, pc}
 8000c20:	20000038 	.word	0x20000038

08000c24 <ssd1306_I2C_Write>:


void ssd1306_I2C_Write(uint8_t address, uint8_t reg, uint8_t data) {
 8000c24:	b580      	push	{r7, lr}
 8000c26:	b086      	sub	sp, #24
 8000c28:	af02      	add	r7, sp, #8
 8000c2a:	4603      	mov	r3, r0
 8000c2c:	71fb      	strb	r3, [r7, #7]
 8000c2e:	460b      	mov	r3, r1
 8000c30:	71bb      	strb	r3, [r7, #6]
 8000c32:	4613      	mov	r3, r2
 8000c34:	717b      	strb	r3, [r7, #5]
	uint8_t dt[2];
	dt[0] = reg;
 8000c36:	79bb      	ldrb	r3, [r7, #6]
 8000c38:	733b      	strb	r3, [r7, #12]
	dt[1] = data;
 8000c3a:	797b      	ldrb	r3, [r7, #5]
 8000c3c:	737b      	strb	r3, [r7, #13]
	HAL_I2C_Master_Transmit(&hi2c1, address, dt, 2, 10);
 8000c3e:	79fb      	ldrb	r3, [r7, #7]
 8000c40:	b299      	uxth	r1, r3
 8000c42:	f107 020c 	add.w	r2, r7, #12
 8000c46:	230a      	movs	r3, #10
 8000c48:	9300      	str	r3, [sp, #0]
 8000c4a:	2302      	movs	r3, #2
 8000c4c:	4803      	ldr	r0, [pc, #12]	; (8000c5c <ssd1306_I2C_Write+0x38>)
 8000c4e:	f000 fced 	bl	800162c <HAL_I2C_Master_Transmit>
}
 8000c52:	bf00      	nop
 8000c54:	3710      	adds	r7, #16
 8000c56:	46bd      	mov	sp, r7
 8000c58:	bd80      	pop	{r7, pc}
 8000c5a:	bf00      	nop
 8000c5c:	20000038 	.word	0x20000038

08000c60 <HAL_MspInit>:
/* USER CODE END 0 */
/**
  * Initializes the Global MSP.
  */
void HAL_MspInit(void)
{
 8000c60:	b480      	push	{r7}
 8000c62:	b083      	sub	sp, #12
 8000c64:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MspInit 0 */

  /* USER CODE END MspInit 0 */

  __HAL_RCC_AFIO_CLK_ENABLE();
 8000c66:	4b0e      	ldr	r3, [pc, #56]	; (8000ca0 <HAL_MspInit+0x40>)
 8000c68:	699b      	ldr	r3, [r3, #24]
 8000c6a:	4a0d      	ldr	r2, [pc, #52]	; (8000ca0 <HAL_MspInit+0x40>)
 8000c6c:	f043 0301 	orr.w	r3, r3, #1
 8000c70:	6193      	str	r3, [r2, #24]
 8000c72:	4b0b      	ldr	r3, [pc, #44]	; (8000ca0 <HAL_MspInit+0x40>)
 8000c74:	699b      	ldr	r3, [r3, #24]
 8000c76:	f003 0301 	and.w	r3, r3, #1
 8000c7a:	607b      	str	r3, [r7, #4]
 8000c7c:	687b      	ldr	r3, [r7, #4]
  __HAL_RCC_PWR_CLK_ENABLE();
 8000c7e:	4b08      	ldr	r3, [pc, #32]	; (8000ca0 <HAL_MspInit+0x40>)
 8000c80:	69db      	ldr	r3, [r3, #28]
 8000c82:	4a07      	ldr	r2, [pc, #28]	; (8000ca0 <HAL_MspInit+0x40>)
 8000c84:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 8000c88:	61d3      	str	r3, [r2, #28]
 8000c8a:	4b05      	ldr	r3, [pc, #20]	; (8000ca0 <HAL_MspInit+0x40>)
 8000c8c:	69db      	ldr	r3, [r3, #28]
 8000c8e:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8000c92:	603b      	str	r3, [r7, #0]
 8000c94:	683b      	ldr	r3, [r7, #0]
  /* System interrupt init*/

  /* USER CODE BEGIN MspInit 1 */

  /* USER CODE END MspInit 1 */
}
 8000c96:	bf00      	nop
 8000c98:	370c      	adds	r7, #12
 8000c9a:	46bd      	mov	sp, r7
 8000c9c:	bc80      	pop	{r7}
 8000c9e:	4770      	bx	lr
 8000ca0:	40021000 	.word	0x40021000

08000ca4 <HAL_I2C_MspInit>:
* This function configures the hardware resources used in this example
* @param hi2c: I2C handle pointer
* @retval None
*/
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
{
 8000ca4:	b580      	push	{r7, lr}
 8000ca6:	b088      	sub	sp, #32
 8000ca8:	af00      	add	r7, sp, #0
 8000caa:	6078      	str	r0, [r7, #4]
  GPIO_InitTypeDef GPIO_InitStruct = {0};
 8000cac:	f107 0310 	add.w	r3, r7, #16
 8000cb0:	2200      	movs	r2, #0
 8000cb2:	601a      	str	r2, [r3, #0]
 8000cb4:	605a      	str	r2, [r3, #4]
 8000cb6:	609a      	str	r2, [r3, #8]
 8000cb8:	60da      	str	r2, [r3, #12]
  if(hi2c->Instance==I2C1)
 8000cba:	687b      	ldr	r3, [r7, #4]
 8000cbc:	681b      	ldr	r3, [r3, #0]
 8000cbe:	4a15      	ldr	r2, [pc, #84]	; (8000d14 <HAL_I2C_MspInit+0x70>)
 8000cc0:	4293      	cmp	r3, r2
 8000cc2:	d123      	bne.n	8000d0c <HAL_I2C_MspInit+0x68>
  {
  /* USER CODE BEGIN I2C1_MspInit 0 */

  /* USER CODE END I2C1_MspInit 0 */

    __HAL_RCC_GPIOB_CLK_ENABLE();
 8000cc4:	4b14      	ldr	r3, [pc, #80]	; (8000d18 <HAL_I2C_MspInit+0x74>)
 8000cc6:	699b      	ldr	r3, [r3, #24]
 8000cc8:	4a13      	ldr	r2, [pc, #76]	; (8000d18 <HAL_I2C_MspInit+0x74>)
 8000cca:	f043 0308 	orr.w	r3, r3, #8
 8000cce:	6193      	str	r3, [r2, #24]
 8000cd0:	4b11      	ldr	r3, [pc, #68]	; (8000d18 <HAL_I2C_MspInit+0x74>)
 8000cd2:	699b      	ldr	r3, [r3, #24]
 8000cd4:	f003 0308 	and.w	r3, r3, #8
 8000cd8:	60fb      	str	r3, [r7, #12]
 8000cda:	68fb      	ldr	r3, [r7, #12]
    /**I2C1 GPIO Configuration
    PB6     ------> I2C1_SCL
    PB7     ------> I2C1_SDA
    */
    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
 8000cdc:	23c0      	movs	r3, #192	; 0xc0
 8000cde:	613b      	str	r3, [r7, #16]
    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
 8000ce0:	2312      	movs	r3, #18
 8000ce2:	617b      	str	r3, [r7, #20]
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
 8000ce4:	2303      	movs	r3, #3
 8000ce6:	61fb      	str	r3, [r7, #28]
    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
 8000ce8:	f107 0310 	add.w	r3, r7, #16
 8000cec:	4619      	mov	r1, r3
 8000cee:	480b      	ldr	r0, [pc, #44]	; (8000d1c <HAL_I2C_MspInit+0x78>)
 8000cf0:	f000 f9d4 	bl	800109c <HAL_GPIO_Init>

    /* Peripheral clock enable */
    __HAL_RCC_I2C1_CLK_ENABLE();
 8000cf4:	4b08      	ldr	r3, [pc, #32]	; (8000d18 <HAL_I2C_MspInit+0x74>)
 8000cf6:	69db      	ldr	r3, [r3, #28]
 8000cf8:	4a07      	ldr	r2, [pc, #28]	; (8000d18 <HAL_I2C_MspInit+0x74>)
 8000cfa:	f443 1300 	orr.w	r3, r3, #2097152	; 0x200000
 8000cfe:	61d3      	str	r3, [r2, #28]
 8000d00:	4b05      	ldr	r3, [pc, #20]	; (8000d18 <HAL_I2C_MspInit+0x74>)
 8000d02:	69db      	ldr	r3, [r3, #28]
 8000d04:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
 8000d08:	60bb      	str	r3, [r7, #8]
 8000d0a:	68bb      	ldr	r3, [r7, #8]
  /* USER CODE BEGIN I2C1_MspInit 1 */

  /* USER CODE END I2C1_MspInit 1 */
  }

}
 8000d0c:	bf00      	nop
 8000d0e:	3720      	adds	r7, #32
 8000d10:	46bd      	mov	sp, r7
 8000d12:	bd80      	pop	{r7, pc}
 8000d14:	40005400 	.word	0x40005400
 8000d18:	40021000 	.word	0x40021000
 8000d1c:	40010c00 	.word	0x40010c00

08000d20 <NMI_Handler>:
/******************************************************************************/
/**
  * @brief This function handles Non maskable interrupt.
  */
void NMI_Handler(void)
{
 8000d20:	b480      	push	{r7}
 8000d22:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN NonMaskableInt_IRQn 0 */

  /* USER CODE END NonMaskableInt_IRQn 0 */
  /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
  while (1)
 8000d24:	e7fe      	b.n	8000d24 <NMI_Handler+0x4>

08000d26 <HardFault_Handler>:

/**
  * @brief This function handles Hard fault interrupt.
  */
void HardFault_Handler(void)
{
 8000d26:	b480      	push	{r7}
 8000d28:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN HardFault_IRQn 0 */

  /* USER CODE END HardFault_IRQn 0 */
  while (1)
 8000d2a:	e7fe      	b.n	8000d2a <HardFault_Handler+0x4>

08000d2c <MemManage_Handler>:

/**
  * @brief This function handles Memory management fault.
  */
void MemManage_Handler(void)
{
 8000d2c:	b480      	push	{r7}
 8000d2e:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN MemoryManagement_IRQn 0 */

  /* USER CODE END MemoryManagement_IRQn 0 */
  while (1)
 8000d30:	e7fe      	b.n	8000d30 <MemManage_Handler+0x4>

08000d32 <BusFault_Handler>:

/**
  * @brief This function handles Prefetch fault, memory access fault.
  */
void BusFault_Handler(void)
{
 8000d32:	b480      	push	{r7}
 8000d34:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN BusFault_IRQn 0 */

  /* USER CODE END BusFault_IRQn 0 */
  while (1)
 8000d36:	e7fe      	b.n	8000d36 <BusFault_Handler+0x4>

08000d38 <UsageFault_Handler>:

/**
  * @brief This function handles Undefined instruction or illegal state.
  */
void UsageFault_Handler(void)
{
 8000d38:	b480      	push	{r7}
 8000d3a:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN UsageFault_IRQn 0 */

  /* USER CODE END UsageFault_IRQn 0 */
  while (1)
 8000d3c:	e7fe      	b.n	8000d3c <UsageFault_Handler+0x4>

08000d3e <SVC_Handler>:

/**
  * @brief This function handles System service call via SWI instruction.
  */
void SVC_Handler(void)
{
 8000d3e:	b480      	push	{r7}
 8000d40:	af00      	add	r7, sp, #0

  /* USER CODE END SVCall_IRQn 0 */
  /* USER CODE BEGIN SVCall_IRQn 1 */

  /* USER CODE END SVCall_IRQn 1 */
}
 8000d42:	bf00      	nop
 8000d44:	46bd      	mov	sp, r7
 8000d46:	bc80      	pop	{r7}
 8000d48:	4770      	bx	lr

08000d4a <DebugMon_Handler>:

/**
  * @brief This function handles Debug monitor.
  */
void DebugMon_Handler(void)
{
 8000d4a:	b480      	push	{r7}
 8000d4c:	af00      	add	r7, sp, #0

  /* USER CODE END DebugMonitor_IRQn 0 */
  /* USER CODE BEGIN DebugMonitor_IRQn 1 */

  /* USER CODE END DebugMonitor_IRQn 1 */
}
 8000d4e:	bf00      	nop
 8000d50:	46bd      	mov	sp, r7
 8000d52:	bc80      	pop	{r7}
 8000d54:	4770      	bx	lr

08000d56 <PendSV_Handler>:

/**
  * @brief This function handles Pendable request for system service.
  */
void PendSV_Handler(void)
{
 8000d56:	b480      	push	{r7}
 8000d58:	af00      	add	r7, sp, #0

  /* USER CODE END PendSV_IRQn 0 */
  /* USER CODE BEGIN PendSV_IRQn 1 */

  /* USER CODE END PendSV_IRQn 1 */
}
 8000d5a:	bf00      	nop
 8000d5c:	46bd      	mov	sp, r7
 8000d5e:	bc80      	pop	{r7}
 8000d60:	4770      	bx	lr

08000d62 <SysTick_Handler>:

/**
  * @brief This function handles System tick timer.
  */
void SysTick_Handler(void)
{
 8000d62:	b580      	push	{r7, lr}
 8000d64:	af00      	add	r7, sp, #0
  /* USER CODE BEGIN SysTick_IRQn 0 */

  /* USER CODE END SysTick_IRQn 0 */
  HAL_IncTick();
 8000d66:	f000 f875 	bl	8000e54 <HAL_IncTick>
  /* USER CODE BEGIN SysTick_IRQn 1 */

  /* USER CODE END SysTick_IRQn 1 */
}
 8000d6a:	bf00      	nop
 8000d6c:	bd80      	pop	{r7, pc}

08000d6e <SystemInit>:
  * @note   This function should be used only after reset.
  * @param  None
  * @retval None
  */
void SystemInit (void)
{
 8000d6e:	b480      	push	{r7}
 8000d70:	af00      	add	r7, sp, #0

  /* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#endif /* USER_VECT_TAB_ADDRESS */
}
 8000d72:	bf00      	nop
 8000d74:	46bd      	mov	sp, r7
 8000d76:	bc80      	pop	{r7}
 8000d78:	4770      	bx	lr
	...

08000d7c <Reset_Handler>:
  .weak Reset_Handler
  .type Reset_Handler, %function
Reset_Handler:

/* Call the clock system initialization function.*/
    bl  SystemInit
 8000d7c:	f7ff fff7 	bl	8000d6e <SystemInit>

/* Copy the data segment initializers from flash to SRAM */
  ldr r0, =_sdata
 8000d80:	480b      	ldr	r0, [pc, #44]	; (8000db0 <LoopFillZerobss+0xe>)
  ldr r1, =_edata
 8000d82:	490c      	ldr	r1, [pc, #48]	; (8000db4 <LoopFillZerobss+0x12>)
  ldr r2, =_sidata
 8000d84:	4a0c      	ldr	r2, [pc, #48]	; (8000db8 <LoopFillZerobss+0x16>)
  movs r3, #0
 8000d86:	2300      	movs	r3, #0
  b LoopCopyDataInit
 8000d88:	e002      	b.n	8000d90 <LoopCopyDataInit>

08000d8a <CopyDataInit>:

CopyDataInit:
  ldr r4, [r2, r3]
 8000d8a:	58d4      	ldr	r4, [r2, r3]
  str r4, [r0, r3]
 8000d8c:	50c4      	str	r4, [r0, r3]
  adds r3, r3, #4
 8000d8e:	3304      	adds	r3, #4

08000d90 <LoopCopyDataInit>:

LoopCopyDataInit:
  adds r4, r0, r3
 8000d90:	18c4      	adds	r4, r0, r3
  cmp r4, r1
 8000d92:	428c      	cmp	r4, r1
  bcc CopyDataInit
 8000d94:	d3f9      	bcc.n	8000d8a <CopyDataInit>
  
/* Zero fill the bss segment. */
  ldr r2, =_sbss
 8000d96:	4a09      	ldr	r2, [pc, #36]	; (8000dbc <LoopFillZerobss+0x1a>)
  ldr r4, =_ebss
 8000d98:	4c09      	ldr	r4, [pc, #36]	; (8000dc0 <LoopFillZerobss+0x1e>)
  movs r3, #0
 8000d9a:	2300      	movs	r3, #0
  b LoopFillZerobss
 8000d9c:	e001      	b.n	8000da2 <LoopFillZerobss>

08000d9e <FillZerobss>:

FillZerobss:
  str  r3, [r2]
 8000d9e:	6013      	str	r3, [r2, #0]
  adds r2, r2, #4
 8000da0:	3204      	adds	r2, #4

08000da2 <LoopFillZerobss>:

LoopFillZerobss:
  cmp r2, r4
 8000da2:	42a2      	cmp	r2, r4
  bcc FillZerobss
 8000da4:	d3fb      	bcc.n	8000d9e <FillZerobss>

/* Call static constructors */
    bl __libc_init_array
 8000da6:	f001 fd27 	bl	80027f8 <__libc_init_array>
/* Call the application's entry point.*/
  bl main
 8000daa:	f7ff f9cf 	bl	800014c <main>
  bx lr
 8000dae:	4770      	bx	lr
  ldr r0, =_sdata
 8000db0:	20000000 	.word	0x20000000
  ldr r1, =_edata
 8000db4:	2000001c 	.word	0x2000001c
  ldr r2, =_sidata
 8000db8:	08004990 	.word	0x08004990
  ldr r2, =_sbss
 8000dbc:	2000001c 	.word	0x2000001c
  ldr r4, =_ebss
 8000dc0:	200004a0 	.word	0x200004a0

08000dc4 <ADC1_2_IRQHandler>:
 * @retval : None
*/
    .section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
  b Infinite_Loop
 8000dc4:	e7fe      	b.n	8000dc4 <ADC1_2_IRQHandler>
	...

08000dc8 <HAL_Init>:
  *         need to ensure that the SysTick time base is always set to 1 millisecond
  *         to have correct HAL operation.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_Init(void)
{
 8000dc8:	b580      	push	{r7, lr}
 8000dca:	af00      	add	r7, sp, #0
    defined(STM32F102x6) || defined(STM32F102xB) || \
    defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || defined(STM32F103xG) || \
    defined(STM32F105xC) || defined(STM32F107xC)

  /* Prefetch buffer is not available on value line devices */
  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 8000dcc:	4b08      	ldr	r3, [pc, #32]	; (8000df0 <HAL_Init+0x28>)
 8000dce:	681b      	ldr	r3, [r3, #0]
 8000dd0:	4a07      	ldr	r2, [pc, #28]	; (8000df0 <HAL_Init+0x28>)
 8000dd2:	f043 0310 	orr.w	r3, r3, #16
 8000dd6:	6013      	str	r3, [r2, #0]
#endif
#endif /* PREFETCH_ENABLE */

  /* Set Interrupt Group Priority */
  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
 8000dd8:	2003      	movs	r0, #3
 8000dda:	f000 f92b 	bl	8001034 <HAL_NVIC_SetPriorityGrouping>

  /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
  HAL_InitTick(TICK_INT_PRIORITY);
 8000dde:	200f      	movs	r0, #15
 8000de0:	f000 f808 	bl	8000df4 <HAL_InitTick>

  /* Init the low level hardware */
  HAL_MspInit();
 8000de4:	f7ff ff3c 	bl	8000c60 <HAL_MspInit>

  /* Return function status */
  return HAL_OK;
 8000de8:	2300      	movs	r3, #0
}
 8000dea:	4618      	mov	r0, r3
 8000dec:	bd80      	pop	{r7, pc}
 8000dee:	bf00      	nop
 8000df0:	40022000 	.word	0x40022000

08000df4 <HAL_InitTick>:
  *       implementation  in user file.
  * @param TickPriority Tick interrupt priority.
  * @retval HAL status
  */
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
 8000df4:	b580      	push	{r7, lr}
 8000df6:	b082      	sub	sp, #8
 8000df8:	af00      	add	r7, sp, #0
 8000dfa:	6078      	str	r0, [r7, #4]
  /* Configure the SysTick to have interrupt in 1ms time basis*/
  if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
 8000dfc:	4b12      	ldr	r3, [pc, #72]	; (8000e48 <HAL_InitTick+0x54>)
 8000dfe:	681a      	ldr	r2, [r3, #0]
 8000e00:	4b12      	ldr	r3, [pc, #72]	; (8000e4c <HAL_InitTick+0x58>)
 8000e02:	781b      	ldrb	r3, [r3, #0]
 8000e04:	4619      	mov	r1, r3
 8000e06:	f44f 737a 	mov.w	r3, #1000	; 0x3e8
 8000e0a:	fbb3 f3f1 	udiv	r3, r3, r1
 8000e0e:	fbb2 f3f3 	udiv	r3, r2, r3
 8000e12:	4618      	mov	r0, r3
 8000e14:	f000 f935 	bl	8001082 <HAL_SYSTICK_Config>
 8000e18:	4603      	mov	r3, r0
 8000e1a:	2b00      	cmp	r3, #0
 8000e1c:	d001      	beq.n	8000e22 <HAL_InitTick+0x2e>
  {
    return HAL_ERROR;
 8000e1e:	2301      	movs	r3, #1
 8000e20:	e00e      	b.n	8000e40 <HAL_InitTick+0x4c>
  }

  /* Configure the SysTick IRQ priority */
  if (TickPriority < (1UL << __NVIC_PRIO_BITS))
 8000e22:	687b      	ldr	r3, [r7, #4]
 8000e24:	2b0f      	cmp	r3, #15
 8000e26:	d80a      	bhi.n	8000e3e <HAL_InitTick+0x4a>
  {
    HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
 8000e28:	2200      	movs	r2, #0
 8000e2a:	6879      	ldr	r1, [r7, #4]
 8000e2c:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 8000e30:	f000 f90b 	bl	800104a <HAL_NVIC_SetPriority>
    uwTickPrio = TickPriority;
 8000e34:	4a06      	ldr	r2, [pc, #24]	; (8000e50 <HAL_InitTick+0x5c>)
 8000e36:	687b      	ldr	r3, [r7, #4]
 8000e38:	6013      	str	r3, [r2, #0]
  {
    return HAL_ERROR;
  }

  /* Return function status */
  return HAL_OK;
 8000e3a:	2300      	movs	r3, #0
 8000e3c:	e000      	b.n	8000e40 <HAL_InitTick+0x4c>
    return HAL_ERROR;
 8000e3e:	2301      	movs	r3, #1
}
 8000e40:	4618      	mov	r0, r3
 8000e42:	3708      	adds	r7, #8
 8000e44:	46bd      	mov	sp, r7
 8000e46:	bd80      	pop	{r7, pc}
 8000e48:	20000010 	.word	0x20000010
 8000e4c:	20000018 	.word	0x20000018
 8000e50:	20000014 	.word	0x20000014

08000e54 <HAL_IncTick>:
  * @note This function is declared as __weak to be overwritten in case of other
  *      implementations in user file.
  * @retval None
  */
__weak void HAL_IncTick(void)
{
 8000e54:	b480      	push	{r7}
 8000e56:	af00      	add	r7, sp, #0
  uwTick += uwTickFreq;
 8000e58:	4b05      	ldr	r3, [pc, #20]	; (8000e70 <HAL_IncTick+0x1c>)
 8000e5a:	781b      	ldrb	r3, [r3, #0]
 8000e5c:	461a      	mov	r2, r3
 8000e5e:	4b05      	ldr	r3, [pc, #20]	; (8000e74 <HAL_IncTick+0x20>)
 8000e60:	681b      	ldr	r3, [r3, #0]
 8000e62:	4413      	add	r3, r2
 8000e64:	4a03      	ldr	r2, [pc, #12]	; (8000e74 <HAL_IncTick+0x20>)
 8000e66:	6013      	str	r3, [r2, #0]
}
 8000e68:	bf00      	nop
 8000e6a:	46bd      	mov	sp, r7
 8000e6c:	bc80      	pop	{r7}
 8000e6e:	4770      	bx	lr
 8000e70:	20000018 	.word	0x20000018
 8000e74:	2000049c 	.word	0x2000049c

08000e78 <HAL_GetTick>:
  * @note  This function is declared as __weak to be overwritten in case of other
  *       implementations in user file.
  * @retval tick value
  */
__weak uint32_t HAL_GetTick(void)
{
 8000e78:	b480      	push	{r7}
 8000e7a:	af00      	add	r7, sp, #0
  return uwTick;
 8000e7c:	4b02      	ldr	r3, [pc, #8]	; (8000e88 <HAL_GetTick+0x10>)
 8000e7e:	681b      	ldr	r3, [r3, #0]
}
 8000e80:	4618      	mov	r0, r3
 8000e82:	46bd      	mov	sp, r7
 8000e84:	bc80      	pop	{r7}
 8000e86:	4770      	bx	lr
 8000e88:	2000049c 	.word	0x2000049c

08000e8c <HAL_Delay>:
  *       implementations in user file.
  * @param Delay specifies the delay time length, in milliseconds.
  * @retval None
  */
__weak void HAL_Delay(uint32_t Delay)
{
 8000e8c:	b580      	push	{r7, lr}
 8000e8e:	b084      	sub	sp, #16
 8000e90:	af00      	add	r7, sp, #0
 8000e92:	6078      	str	r0, [r7, #4]
  uint32_t tickstart = HAL_GetTick();
 8000e94:	f7ff fff0 	bl	8000e78 <HAL_GetTick>
 8000e98:	60b8      	str	r0, [r7, #8]
  uint32_t wait = Delay;
 8000e9a:	687b      	ldr	r3, [r7, #4]
 8000e9c:	60fb      	str	r3, [r7, #12]

  /* Add a freq to guarantee minimum wait */
  if (wait < HAL_MAX_DELAY)
 8000e9e:	68fb      	ldr	r3, [r7, #12]
 8000ea0:	f1b3 3fff 	cmp.w	r3, #4294967295	; 0xffffffff
 8000ea4:	d005      	beq.n	8000eb2 <HAL_Delay+0x26>
  {
    wait += (uint32_t)(uwTickFreq);
 8000ea6:	4b0a      	ldr	r3, [pc, #40]	; (8000ed0 <HAL_Delay+0x44>)
 8000ea8:	781b      	ldrb	r3, [r3, #0]
 8000eaa:	461a      	mov	r2, r3
 8000eac:	68fb      	ldr	r3, [r7, #12]
 8000eae:	4413      	add	r3, r2
 8000eb0:	60fb      	str	r3, [r7, #12]
  }

  while ((HAL_GetTick() - tickstart) < wait)
 8000eb2:	bf00      	nop
 8000eb4:	f7ff ffe0 	bl	8000e78 <HAL_GetTick>
 8000eb8:	4602      	mov	r2, r0
 8000eba:	68bb      	ldr	r3, [r7, #8]
 8000ebc:	1ad3      	subs	r3, r2, r3
 8000ebe:	68fa      	ldr	r2, [r7, #12]
 8000ec0:	429a      	cmp	r2, r3
 8000ec2:	d8f7      	bhi.n	8000eb4 <HAL_Delay+0x28>
  {
  }
}
 8000ec4:	bf00      	nop
 8000ec6:	bf00      	nop
 8000ec8:	3710      	adds	r7, #16
 8000eca:	46bd      	mov	sp, r7
 8000ecc:	bd80      	pop	{r7, pc}
 8000ece:	bf00      	nop
 8000ed0:	20000018 	.word	0x20000018

08000ed4 <__NVIC_SetPriorityGrouping>:
           In case of a conflict between priority grouping and available
           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
  \param [in]      PriorityGroup  Priority grouping field.
 */
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 8000ed4:	b480      	push	{r7}
 8000ed6:	b085      	sub	sp, #20
 8000ed8:	af00      	add	r7, sp, #0
 8000eda:	6078      	str	r0, [r7, #4]
  uint32_t reg_value;
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
 8000edc:	687b      	ldr	r3, [r7, #4]
 8000ede:	f003 0307 	and.w	r3, r3, #7
 8000ee2:	60fb      	str	r3, [r7, #12]

  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
 8000ee4:	4b0c      	ldr	r3, [pc, #48]	; (8000f18 <__NVIC_SetPriorityGrouping+0x44>)
 8000ee6:	68db      	ldr	r3, [r3, #12]
 8000ee8:	60bb      	str	r3, [r7, #8]
  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
 8000eea:	68ba      	ldr	r2, [r7, #8]
 8000eec:	f64f 03ff 	movw	r3, #63743	; 0xf8ff
 8000ef0:	4013      	ands	r3, r2
 8000ef2:	60bb      	str	r3, [r7, #8]
  reg_value  =  (reg_value                                   |
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
                (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) );               /* Insert write key and priority group */
 8000ef4:	68fb      	ldr	r3, [r7, #12]
 8000ef6:	021a      	lsls	r2, r3, #8
                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
 8000ef8:	68bb      	ldr	r3, [r7, #8]
 8000efa:	4313      	orrs	r3, r2
  reg_value  =  (reg_value                                   |
 8000efc:	f043 63bf 	orr.w	r3, r3, #100139008	; 0x5f80000
 8000f00:	f443 3300 	orr.w	r3, r3, #131072	; 0x20000
 8000f04:	60bb      	str	r3, [r7, #8]
  SCB->AIRCR =  reg_value;
 8000f06:	4a04      	ldr	r2, [pc, #16]	; (8000f18 <__NVIC_SetPriorityGrouping+0x44>)
 8000f08:	68bb      	ldr	r3, [r7, #8]
 8000f0a:	60d3      	str	r3, [r2, #12]
}
 8000f0c:	bf00      	nop
 8000f0e:	3714      	adds	r7, #20
 8000f10:	46bd      	mov	sp, r7
 8000f12:	bc80      	pop	{r7}
 8000f14:	4770      	bx	lr
 8000f16:	bf00      	nop
 8000f18:	e000ed00 	.word	0xe000ed00

08000f1c <__NVIC_GetPriorityGrouping>:
  \brief   Get Priority Grouping
  \details Reads the priority grouping field from the NVIC Interrupt Controller.
  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
 */
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
 8000f1c:	b480      	push	{r7}
 8000f1e:	af00      	add	r7, sp, #0
  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
 8000f20:	4b04      	ldr	r3, [pc, #16]	; (8000f34 <__NVIC_GetPriorityGrouping+0x18>)
 8000f22:	68db      	ldr	r3, [r3, #12]
 8000f24:	0a1b      	lsrs	r3, r3, #8
 8000f26:	f003 0307 	and.w	r3, r3, #7
}
 8000f2a:	4618      	mov	r0, r3
 8000f2c:	46bd      	mov	sp, r7
 8000f2e:	bc80      	pop	{r7}
 8000f30:	4770      	bx	lr
 8000f32:	bf00      	nop
 8000f34:	e000ed00 	.word	0xe000ed00

08000f38 <__NVIC_SetPriority>:
  \param [in]      IRQn  Interrupt number.
  \param [in]  priority  Priority to set.
  \note    The priority cannot be set for every processor exception.
 */
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
 8000f38:	b480      	push	{r7}
 8000f3a:	b083      	sub	sp, #12
 8000f3c:	af00      	add	r7, sp, #0
 8000f3e:	4603      	mov	r3, r0
 8000f40:	6039      	str	r1, [r7, #0]
 8000f42:	71fb      	strb	r3, [r7, #7]
  if ((int32_t)(IRQn) >= 0)
 8000f44:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8000f48:	2b00      	cmp	r3, #0
 8000f4a:	db0a      	blt.n	8000f62 <__NVIC_SetPriority+0x2a>
  {
    NVIC->IP[((uint32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000f4c:	683b      	ldr	r3, [r7, #0]
 8000f4e:	b2da      	uxtb	r2, r3
 8000f50:	490c      	ldr	r1, [pc, #48]	; (8000f84 <__NVIC_SetPriority+0x4c>)
 8000f52:	f997 3007 	ldrsb.w	r3, [r7, #7]
 8000f56:	0112      	lsls	r2, r2, #4
 8000f58:	b2d2      	uxtb	r2, r2
 8000f5a:	440b      	add	r3, r1
 8000f5c:	f883 2300 	strb.w	r2, [r3, #768]	; 0x300
  }
  else
  {
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
  }
}
 8000f60:	e00a      	b.n	8000f78 <__NVIC_SetPriority+0x40>
    SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
 8000f62:	683b      	ldr	r3, [r7, #0]
 8000f64:	b2da      	uxtb	r2, r3
 8000f66:	4908      	ldr	r1, [pc, #32]	; (8000f88 <__NVIC_SetPriority+0x50>)
 8000f68:	79fb      	ldrb	r3, [r7, #7]
 8000f6a:	f003 030f 	and.w	r3, r3, #15
 8000f6e:	3b04      	subs	r3, #4
 8000f70:	0112      	lsls	r2, r2, #4
 8000f72:	b2d2      	uxtb	r2, r2
 8000f74:	440b      	add	r3, r1
 8000f76:	761a      	strb	r2, [r3, #24]
}
 8000f78:	bf00      	nop
 8000f7a:	370c      	adds	r7, #12
 8000f7c:	46bd      	mov	sp, r7
 8000f7e:	bc80      	pop	{r7}
 8000f80:	4770      	bx	lr
 8000f82:	bf00      	nop
 8000f84:	e000e100 	.word	0xe000e100
 8000f88:	e000ed00 	.word	0xe000ed00

08000f8c <NVIC_EncodePriority>:
  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
  \param [in]       SubPriority  Subpriority value (starting from 0).
  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
 */
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
 8000f8c:	b480      	push	{r7}
 8000f8e:	b089      	sub	sp, #36	; 0x24
 8000f90:	af00      	add	r7, sp, #0
 8000f92:	60f8      	str	r0, [r7, #12]
 8000f94:	60b9      	str	r1, [r7, #8]
 8000f96:	607a      	str	r2, [r7, #4]
  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
 8000f98:	68fb      	ldr	r3, [r7, #12]
 8000f9a:	f003 0307 	and.w	r3, r3, #7
 8000f9e:	61fb      	str	r3, [r7, #28]
  uint32_t PreemptPriorityBits;
  uint32_t SubPriorityBits;

  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
 8000fa0:	69fb      	ldr	r3, [r7, #28]
 8000fa2:	f1c3 0307 	rsb	r3, r3, #7
 8000fa6:	2b04      	cmp	r3, #4
 8000fa8:	bf28      	it	cs
 8000faa:	2304      	movcs	r3, #4
 8000fac:	61bb      	str	r3, [r7, #24]
  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
 8000fae:	69fb      	ldr	r3, [r7, #28]
 8000fb0:	3304      	adds	r3, #4
 8000fb2:	2b06      	cmp	r3, #6
 8000fb4:	d902      	bls.n	8000fbc <NVIC_EncodePriority+0x30>
 8000fb6:	69fb      	ldr	r3, [r7, #28]
 8000fb8:	3b03      	subs	r3, #3
 8000fba:	e000      	b.n	8000fbe <NVIC_EncodePriority+0x32>
 8000fbc:	2300      	movs	r3, #0
 8000fbe:	617b      	str	r3, [r7, #20]

  return (
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000fc0:	f04f 32ff 	mov.w	r2, #4294967295	; 0xffffffff
 8000fc4:	69bb      	ldr	r3, [r7, #24]
 8000fc6:	fa02 f303 	lsl.w	r3, r2, r3
 8000fca:	43da      	mvns	r2, r3
 8000fcc:	68bb      	ldr	r3, [r7, #8]
 8000fce:	401a      	ands	r2, r3
 8000fd0:	697b      	ldr	r3, [r7, #20]
 8000fd2:	409a      	lsls	r2, r3
           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
 8000fd4:	f04f 31ff 	mov.w	r1, #4294967295	; 0xffffffff
 8000fd8:	697b      	ldr	r3, [r7, #20]
 8000fda:	fa01 f303 	lsl.w	r3, r1, r3
 8000fde:	43d9      	mvns	r1, r3
 8000fe0:	687b      	ldr	r3, [r7, #4]
 8000fe2:	400b      	ands	r3, r1
           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
 8000fe4:	4313      	orrs	r3, r2
         );
}
 8000fe6:	4618      	mov	r0, r3
 8000fe8:	3724      	adds	r7, #36	; 0x24
 8000fea:	46bd      	mov	sp, r7
 8000fec:	bc80      	pop	{r7}
 8000fee:	4770      	bx	lr

08000ff0 <SysTick_Config>:
  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
           must contain a vendor-specific implementation of this function.
 */
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
 8000ff0:	b580      	push	{r7, lr}
 8000ff2:	b082      	sub	sp, #8
 8000ff4:	af00      	add	r7, sp, #0
 8000ff6:	6078      	str	r0, [r7, #4]
  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
 8000ff8:	687b      	ldr	r3, [r7, #4]
 8000ffa:	3b01      	subs	r3, #1
 8000ffc:	f1b3 7f80 	cmp.w	r3, #16777216	; 0x1000000
 8001000:	d301      	bcc.n	8001006 <SysTick_Config+0x16>
  {
    return (1UL);                                                   /* Reload value impossible */
 8001002:	2301      	movs	r3, #1
 8001004:	e00f      	b.n	8001026 <SysTick_Config+0x36>
  }

  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
 8001006:	4a0a      	ldr	r2, [pc, #40]	; (8001030 <SysTick_Config+0x40>)
 8001008:	687b      	ldr	r3, [r7, #4]
 800100a:	3b01      	subs	r3, #1
 800100c:	6053      	str	r3, [r2, #4]
  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
 800100e:	210f      	movs	r1, #15
 8001010:	f04f 30ff 	mov.w	r0, #4294967295	; 0xffffffff
 8001014:	f7ff ff90 	bl	8000f38 <__NVIC_SetPriority>
  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
 8001018:	4b05      	ldr	r3, [pc, #20]	; (8001030 <SysTick_Config+0x40>)
 800101a:	2200      	movs	r2, #0
 800101c:	609a      	str	r2, [r3, #8]
  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
 800101e:	4b04      	ldr	r3, [pc, #16]	; (8001030 <SysTick_Config+0x40>)
 8001020:	2207      	movs	r2, #7
 8001022:	601a      	str	r2, [r3, #0]
                   SysTick_CTRL_TICKINT_Msk   |
                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
  return (0UL);                                                     /* Function successful */
 8001024:	2300      	movs	r3, #0
}
 8001026:	4618      	mov	r0, r3
 8001028:	3708      	adds	r7, #8
 800102a:	46bd      	mov	sp, r7
 800102c:	bd80      	pop	{r7, pc}
 800102e:	bf00      	nop
 8001030:	e000e010 	.word	0xe000e010

08001034 <HAL_NVIC_SetPriorityGrouping>:
  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ preemption is no more possible. 
  *         The pending IRQ priority will be managed only by the subpriority. 
  * @retval None
  */
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
 8001034:	b580      	push	{r7, lr}
 8001036:	b082      	sub	sp, #8
 8001038:	af00      	add	r7, sp, #0
 800103a:	6078      	str	r0, [r7, #4]
  /* Check the parameters */
  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
  
  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
  NVIC_SetPriorityGrouping(PriorityGroup);
 800103c:	6878      	ldr	r0, [r7, #4]
 800103e:	f7ff ff49 	bl	8000ed4 <__NVIC_SetPriorityGrouping>
}
 8001042:	bf00      	nop
 8001044:	3708      	adds	r7, #8
 8001046:	46bd      	mov	sp, r7
 8001048:	bd80      	pop	{r7, pc}

0800104a <HAL_NVIC_SetPriority>:
  *         This parameter can be a value between 0 and 15
  *         A lower priority value indicates a higher priority.          
  * @retval None
  */
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{ 
 800104a:	b580      	push	{r7, lr}
 800104c:	b086      	sub	sp, #24
 800104e:	af00      	add	r7, sp, #0
 8001050:	4603      	mov	r3, r0
 8001052:	60b9      	str	r1, [r7, #8]
 8001054:	607a      	str	r2, [r7, #4]
 8001056:	73fb      	strb	r3, [r7, #15]
  uint32_t prioritygroup = 0x00U;
 8001058:	2300      	movs	r3, #0
 800105a:	617b      	str	r3, [r7, #20]
  
  /* Check the parameters */
  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
  
  prioritygroup = NVIC_GetPriorityGrouping();
 800105c:	f7ff ff5e 	bl	8000f1c <__NVIC_GetPriorityGrouping>
 8001060:	6178      	str	r0, [r7, #20]
  
  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
 8001062:	687a      	ldr	r2, [r7, #4]
 8001064:	68b9      	ldr	r1, [r7, #8]
 8001066:	6978      	ldr	r0, [r7, #20]
 8001068:	f7ff ff90 	bl	8000f8c <NVIC_EncodePriority>
 800106c:	4602      	mov	r2, r0
 800106e:	f997 300f 	ldrsb.w	r3, [r7, #15]
 8001072:	4611      	mov	r1, r2
 8001074:	4618      	mov	r0, r3
 8001076:	f7ff ff5f 	bl	8000f38 <__NVIC_SetPriority>
}
 800107a:	bf00      	nop
 800107c:	3718      	adds	r7, #24
 800107e:	46bd      	mov	sp, r7
 8001080:	bd80      	pop	{r7, pc}

08001082 <HAL_SYSTICK_Config>:
  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
  * @retval status:  - 0  Function succeeded.
  *                  - 1  Function failed.
  */
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
 8001082:	b580      	push	{r7, lr}
 8001084:	b082      	sub	sp, #8
 8001086:	af00      	add	r7, sp, #0
 8001088:	6078      	str	r0, [r7, #4]
   return SysTick_Config(TicksNumb);
 800108a:	6878      	ldr	r0, [r7, #4]
 800108c:	f7ff ffb0 	bl	8000ff0 <SysTick_Config>
 8001090:	4603      	mov	r3, r0
}
 8001092:	4618      	mov	r0, r3
 8001094:	3708      	adds	r7, #8
 8001096:	46bd      	mov	sp, r7
 8001098:	bd80      	pop	{r7, pc}
	...

0800109c <HAL_GPIO_Init>:
  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
  *         the configuration information for the specified GPIO peripheral.
  * @retval None
  */
void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
 800109c:	b480      	push	{r7}
 800109e:	b08b      	sub	sp, #44	; 0x2c
 80010a0:	af00      	add	r7, sp, #0
 80010a2:	6078      	str	r0, [r7, #4]
 80010a4:	6039      	str	r1, [r7, #0]
  uint32_t position = 0x00u;
 80010a6:	2300      	movs	r3, #0
 80010a8:	627b      	str	r3, [r7, #36]	; 0x24
  uint32_t ioposition;
  uint32_t iocurrent;
  uint32_t temp;
  uint32_t config = 0x00u;
 80010aa:	2300      	movs	r3, #0
 80010ac:	623b      	str	r3, [r7, #32]
  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));

  /* Configure the port pins */
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 80010ae:	e169      	b.n	8001384 <HAL_GPIO_Init+0x2e8>
  {
    /* Get the IO position */
    ioposition = (0x01uL << position);
 80010b0:	2201      	movs	r2, #1
 80010b2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 80010b4:	fa02 f303 	lsl.w	r3, r2, r3
 80010b8:	61fb      	str	r3, [r7, #28]

    /* Get the current IO position */
    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
 80010ba:	683b      	ldr	r3, [r7, #0]
 80010bc:	681b      	ldr	r3, [r3, #0]
 80010be:	69fa      	ldr	r2, [r7, #28]
 80010c0:	4013      	ands	r3, r2
 80010c2:	61bb      	str	r3, [r7, #24]

    if (iocurrent == ioposition)
 80010c4:	69ba      	ldr	r2, [r7, #24]
 80010c6:	69fb      	ldr	r3, [r7, #28]
 80010c8:	429a      	cmp	r2, r3
 80010ca:	f040 8158 	bne.w	800137e <HAL_GPIO_Init+0x2e2>
    {
      /* Check the Alternate function parameters */
      assert_param(IS_GPIO_AF_INSTANCE(GPIOx));

      /* Based on the required mode, filling config variable with MODEy[1:0] and CNFy[3:2] corresponding bits */
      switch (GPIO_Init->Mode)
 80010ce:	683b      	ldr	r3, [r7, #0]
 80010d0:	685b      	ldr	r3, [r3, #4]
 80010d2:	4a9a      	ldr	r2, [pc, #616]	; (800133c <HAL_GPIO_Init+0x2a0>)
 80010d4:	4293      	cmp	r3, r2
 80010d6:	d05e      	beq.n	8001196 <HAL_GPIO_Init+0xfa>
 80010d8:	4a98      	ldr	r2, [pc, #608]	; (800133c <HAL_GPIO_Init+0x2a0>)
 80010da:	4293      	cmp	r3, r2
 80010dc:	d875      	bhi.n	80011ca <HAL_GPIO_Init+0x12e>
 80010de:	4a98      	ldr	r2, [pc, #608]	; (8001340 <HAL_GPIO_Init+0x2a4>)
 80010e0:	4293      	cmp	r3, r2
 80010e2:	d058      	beq.n	8001196 <HAL_GPIO_Init+0xfa>
 80010e4:	4a96      	ldr	r2, [pc, #600]	; (8001340 <HAL_GPIO_Init+0x2a4>)
 80010e6:	4293      	cmp	r3, r2
 80010e8:	d86f      	bhi.n	80011ca <HAL_GPIO_Init+0x12e>
 80010ea:	4a96      	ldr	r2, [pc, #600]	; (8001344 <HAL_GPIO_Init+0x2a8>)
 80010ec:	4293      	cmp	r3, r2
 80010ee:	d052      	beq.n	8001196 <HAL_GPIO_Init+0xfa>
 80010f0:	4a94      	ldr	r2, [pc, #592]	; (8001344 <HAL_GPIO_Init+0x2a8>)
 80010f2:	4293      	cmp	r3, r2
 80010f4:	d869      	bhi.n	80011ca <HAL_GPIO_Init+0x12e>
 80010f6:	4a94      	ldr	r2, [pc, #592]	; (8001348 <HAL_GPIO_Init+0x2ac>)
 80010f8:	4293      	cmp	r3, r2
 80010fa:	d04c      	beq.n	8001196 <HAL_GPIO_Init+0xfa>
 80010fc:	4a92      	ldr	r2, [pc, #584]	; (8001348 <HAL_GPIO_Init+0x2ac>)
 80010fe:	4293      	cmp	r3, r2
 8001100:	d863      	bhi.n	80011ca <HAL_GPIO_Init+0x12e>
 8001102:	4a92      	ldr	r2, [pc, #584]	; (800134c <HAL_GPIO_Init+0x2b0>)
 8001104:	4293      	cmp	r3, r2
 8001106:	d046      	beq.n	8001196 <HAL_GPIO_Init+0xfa>
 8001108:	4a90      	ldr	r2, [pc, #576]	; (800134c <HAL_GPIO_Init+0x2b0>)
 800110a:	4293      	cmp	r3, r2
 800110c:	d85d      	bhi.n	80011ca <HAL_GPIO_Init+0x12e>
 800110e:	2b12      	cmp	r3, #18
 8001110:	d82a      	bhi.n	8001168 <HAL_GPIO_Init+0xcc>
 8001112:	2b12      	cmp	r3, #18
 8001114:	d859      	bhi.n	80011ca <HAL_GPIO_Init+0x12e>
 8001116:	a201      	add	r2, pc, #4	; (adr r2, 800111c <HAL_GPIO_Init+0x80>)
 8001118:	f852 f023 	ldr.w	pc, [r2, r3, lsl #2]
 800111c:	08001197 	.word	0x08001197
 8001120:	08001171 	.word	0x08001171
 8001124:	08001183 	.word	0x08001183
 8001128:	080011c5 	.word	0x080011c5
 800112c:	080011cb 	.word	0x080011cb
 8001130:	080011cb 	.word	0x080011cb
 8001134:	080011cb 	.word	0x080011cb
 8001138:	080011cb 	.word	0x080011cb
 800113c:	080011cb 	.word	0x080011cb
 8001140:	080011cb 	.word	0x080011cb
 8001144:	080011cb 	.word	0x080011cb
 8001148:	080011cb 	.word	0x080011cb
 800114c:	080011cb 	.word	0x080011cb
 8001150:	080011cb 	.word	0x080011cb
 8001154:	080011cb 	.word	0x080011cb
 8001158:	080011cb 	.word	0x080011cb
 800115c:	080011cb 	.word	0x080011cb
 8001160:	08001179 	.word	0x08001179
 8001164:	0800118d 	.word	0x0800118d
 8001168:	4a79      	ldr	r2, [pc, #484]	; (8001350 <HAL_GPIO_Init+0x2b4>)
 800116a:	4293      	cmp	r3, r2
 800116c:	d013      	beq.n	8001196 <HAL_GPIO_Init+0xfa>
          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
          break;

        /* Parameters are checked with assert_param */
        default:
          break;
 800116e:	e02c      	b.n	80011ca <HAL_GPIO_Init+0x12e>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_PP;
 8001170:	683b      	ldr	r3, [r7, #0]
 8001172:	68db      	ldr	r3, [r3, #12]
 8001174:	623b      	str	r3, [r7, #32]
          break;
 8001176:	e029      	b.n	80011cc <HAL_GPIO_Init+0x130>
          config = GPIO_Init->Speed + GPIO_CR_CNF_GP_OUTPUT_OD;
 8001178:	683b      	ldr	r3, [r7, #0]
 800117a:	68db      	ldr	r3, [r3, #12]
 800117c:	3304      	adds	r3, #4
 800117e:	623b      	str	r3, [r7, #32]
          break;
 8001180:	e024      	b.n	80011cc <HAL_GPIO_Init+0x130>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_PP;
 8001182:	683b      	ldr	r3, [r7, #0]
 8001184:	68db      	ldr	r3, [r3, #12]
 8001186:	3308      	adds	r3, #8
 8001188:	623b      	str	r3, [r7, #32]
          break;
 800118a:	e01f      	b.n	80011cc <HAL_GPIO_Init+0x130>
          config = GPIO_Init->Speed + GPIO_CR_CNF_AF_OUTPUT_OD;
 800118c:	683b      	ldr	r3, [r7, #0]
 800118e:	68db      	ldr	r3, [r3, #12]
 8001190:	330c      	adds	r3, #12
 8001192:	623b      	str	r3, [r7, #32]
          break;
 8001194:	e01a      	b.n	80011cc <HAL_GPIO_Init+0x130>
          if (GPIO_Init->Pull == GPIO_NOPULL)
 8001196:	683b      	ldr	r3, [r7, #0]
 8001198:	689b      	ldr	r3, [r3, #8]
 800119a:	2b00      	cmp	r3, #0
 800119c:	d102      	bne.n	80011a4 <HAL_GPIO_Init+0x108>
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_FLOATING;
 800119e:	2304      	movs	r3, #4
 80011a0:	623b      	str	r3, [r7, #32]
          break;
 80011a2:	e013      	b.n	80011cc <HAL_GPIO_Init+0x130>
          else if (GPIO_Init->Pull == GPIO_PULLUP)
 80011a4:	683b      	ldr	r3, [r7, #0]
 80011a6:	689b      	ldr	r3, [r3, #8]
 80011a8:	2b01      	cmp	r3, #1
 80011aa:	d105      	bne.n	80011b8 <HAL_GPIO_Init+0x11c>
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
 80011ac:	2308      	movs	r3, #8
 80011ae:	623b      	str	r3, [r7, #32]
            GPIOx->BSRR = ioposition;
 80011b0:	687b      	ldr	r3, [r7, #4]
 80011b2:	69fa      	ldr	r2, [r7, #28]
 80011b4:	611a      	str	r2, [r3, #16]
          break;
 80011b6:	e009      	b.n	80011cc <HAL_GPIO_Init+0x130>
            config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_INPUT_PU_PD;
 80011b8:	2308      	movs	r3, #8
 80011ba:	623b      	str	r3, [r7, #32]
            GPIOx->BRR = ioposition;
 80011bc:	687b      	ldr	r3, [r7, #4]
 80011be:	69fa      	ldr	r2, [r7, #28]
 80011c0:	615a      	str	r2, [r3, #20]
          break;
 80011c2:	e003      	b.n	80011cc <HAL_GPIO_Init+0x130>
          config = GPIO_CR_MODE_INPUT + GPIO_CR_CNF_ANALOG;
 80011c4:	2300      	movs	r3, #0
 80011c6:	623b      	str	r3, [r7, #32]
          break;
 80011c8:	e000      	b.n	80011cc <HAL_GPIO_Init+0x130>
          break;
 80011ca:	bf00      	nop
      }

      /* Check if the current bit belongs to first half or last half of the pin count number
       in order to address CRH or CRL register*/
      configregister = (iocurrent < GPIO_PIN_8) ? &GPIOx->CRL     : &GPIOx->CRH;
 80011cc:	69bb      	ldr	r3, [r7, #24]
 80011ce:	2bff      	cmp	r3, #255	; 0xff
 80011d0:	d801      	bhi.n	80011d6 <HAL_GPIO_Init+0x13a>
 80011d2:	687b      	ldr	r3, [r7, #4]
 80011d4:	e001      	b.n	80011da <HAL_GPIO_Init+0x13e>
 80011d6:	687b      	ldr	r3, [r7, #4]
 80011d8:	3304      	adds	r3, #4
 80011da:	617b      	str	r3, [r7, #20]
      registeroffset = (iocurrent < GPIO_PIN_8) ? (position << 2u) : ((position - 8u) << 2u);
 80011dc:	69bb      	ldr	r3, [r7, #24]
 80011de:	2bff      	cmp	r3, #255	; 0xff
 80011e0:	d802      	bhi.n	80011e8 <HAL_GPIO_Init+0x14c>
 80011e2:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 80011e4:	009b      	lsls	r3, r3, #2
 80011e6:	e002      	b.n	80011ee <HAL_GPIO_Init+0x152>
 80011e8:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 80011ea:	3b08      	subs	r3, #8
 80011ec:	009b      	lsls	r3, r3, #2
 80011ee:	613b      	str	r3, [r7, #16]

      /* Apply the new configuration of the pin to the register */
      MODIFY_REG((*configregister), ((GPIO_CRL_MODE0 | GPIO_CRL_CNF0) << registeroffset), (config << registeroffset));
 80011f0:	697b      	ldr	r3, [r7, #20]
 80011f2:	681a      	ldr	r2, [r3, #0]
 80011f4:	210f      	movs	r1, #15
 80011f6:	693b      	ldr	r3, [r7, #16]
 80011f8:	fa01 f303 	lsl.w	r3, r1, r3
 80011fc:	43db      	mvns	r3, r3
 80011fe:	401a      	ands	r2, r3
 8001200:	6a39      	ldr	r1, [r7, #32]
 8001202:	693b      	ldr	r3, [r7, #16]
 8001204:	fa01 f303 	lsl.w	r3, r1, r3
 8001208:	431a      	orrs	r2, r3
 800120a:	697b      	ldr	r3, [r7, #20]
 800120c:	601a      	str	r2, [r3, #0]

      /*--------------------- EXTI Mode Configuration ------------------------*/
      /* Configure the External Interrupt or event for the current IO */
      if ((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
 800120e:	683b      	ldr	r3, [r7, #0]
 8001210:	685b      	ldr	r3, [r3, #4]
 8001212:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 8001216:	2b00      	cmp	r3, #0
 8001218:	f000 80b1 	beq.w	800137e <HAL_GPIO_Init+0x2e2>
      {
        /* Enable AFIO Clock */
        __HAL_RCC_AFIO_CLK_ENABLE();
 800121c:	4b4d      	ldr	r3, [pc, #308]	; (8001354 <HAL_GPIO_Init+0x2b8>)
 800121e:	699b      	ldr	r3, [r3, #24]
 8001220:	4a4c      	ldr	r2, [pc, #304]	; (8001354 <HAL_GPIO_Init+0x2b8>)
 8001222:	f043 0301 	orr.w	r3, r3, #1
 8001226:	6193      	str	r3, [r2, #24]
 8001228:	4b4a      	ldr	r3, [pc, #296]	; (8001354 <HAL_GPIO_Init+0x2b8>)
 800122a:	699b      	ldr	r3, [r3, #24]
 800122c:	f003 0301 	and.w	r3, r3, #1
 8001230:	60bb      	str	r3, [r7, #8]
 8001232:	68bb      	ldr	r3, [r7, #8]
        temp = AFIO->EXTICR[position >> 2u];
 8001234:	4a48      	ldr	r2, [pc, #288]	; (8001358 <HAL_GPIO_Init+0x2bc>)
 8001236:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8001238:	089b      	lsrs	r3, r3, #2
 800123a:	3302      	adds	r3, #2
 800123c:	f852 3023 	ldr.w	r3, [r2, r3, lsl #2]
 8001240:	60fb      	str	r3, [r7, #12]
        CLEAR_BIT(temp, (0x0Fu) << (4u * (position & 0x03u)));
 8001242:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8001244:	f003 0303 	and.w	r3, r3, #3
 8001248:	009b      	lsls	r3, r3, #2
 800124a:	220f      	movs	r2, #15
 800124c:	fa02 f303 	lsl.w	r3, r2, r3
 8001250:	43db      	mvns	r3, r3
 8001252:	68fa      	ldr	r2, [r7, #12]
 8001254:	4013      	ands	r3, r2
 8001256:	60fb      	str	r3, [r7, #12]
        SET_BIT(temp, (GPIO_GET_INDEX(GPIOx)) << (4u * (position & 0x03u)));
 8001258:	687b      	ldr	r3, [r7, #4]
 800125a:	4a40      	ldr	r2, [pc, #256]	; (800135c <HAL_GPIO_Init+0x2c0>)
 800125c:	4293      	cmp	r3, r2
 800125e:	d013      	beq.n	8001288 <HAL_GPIO_Init+0x1ec>
 8001260:	687b      	ldr	r3, [r7, #4]
 8001262:	4a3f      	ldr	r2, [pc, #252]	; (8001360 <HAL_GPIO_Init+0x2c4>)
 8001264:	4293      	cmp	r3, r2
 8001266:	d00d      	beq.n	8001284 <HAL_GPIO_Init+0x1e8>
 8001268:	687b      	ldr	r3, [r7, #4]
 800126a:	4a3e      	ldr	r2, [pc, #248]	; (8001364 <HAL_GPIO_Init+0x2c8>)
 800126c:	4293      	cmp	r3, r2
 800126e:	d007      	beq.n	8001280 <HAL_GPIO_Init+0x1e4>
 8001270:	687b      	ldr	r3, [r7, #4]
 8001272:	4a3d      	ldr	r2, [pc, #244]	; (8001368 <HAL_GPIO_Init+0x2cc>)
 8001274:	4293      	cmp	r3, r2
 8001276:	d101      	bne.n	800127c <HAL_GPIO_Init+0x1e0>
 8001278:	2303      	movs	r3, #3
 800127a:	e006      	b.n	800128a <HAL_GPIO_Init+0x1ee>
 800127c:	2304      	movs	r3, #4
 800127e:	e004      	b.n	800128a <HAL_GPIO_Init+0x1ee>
 8001280:	2302      	movs	r3, #2
 8001282:	e002      	b.n	800128a <HAL_GPIO_Init+0x1ee>
 8001284:	2301      	movs	r3, #1
 8001286:	e000      	b.n	800128a <HAL_GPIO_Init+0x1ee>
 8001288:	2300      	movs	r3, #0
 800128a:	6a7a      	ldr	r2, [r7, #36]	; 0x24
 800128c:	f002 0203 	and.w	r2, r2, #3
 8001290:	0092      	lsls	r2, r2, #2
 8001292:	4093      	lsls	r3, r2
 8001294:	68fa      	ldr	r2, [r7, #12]
 8001296:	4313      	orrs	r3, r2
 8001298:	60fb      	str	r3, [r7, #12]
        AFIO->EXTICR[position >> 2u] = temp;
 800129a:	492f      	ldr	r1, [pc, #188]	; (8001358 <HAL_GPIO_Init+0x2bc>)
 800129c:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 800129e:	089b      	lsrs	r3, r3, #2
 80012a0:	3302      	adds	r3, #2
 80012a2:	68fa      	ldr	r2, [r7, #12]
 80012a4:	f841 2023 	str.w	r2, [r1, r3, lsl #2]


        /* Enable or disable the rising trigger */
        if ((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
 80012a8:	683b      	ldr	r3, [r7, #0]
 80012aa:	685b      	ldr	r3, [r3, #4]
 80012ac:	f403 1380 	and.w	r3, r3, #1048576	; 0x100000
 80012b0:	2b00      	cmp	r3, #0
 80012b2:	d006      	beq.n	80012c2 <HAL_GPIO_Init+0x226>
        {
          SET_BIT(EXTI->RTSR, iocurrent);
 80012b4:	4b2d      	ldr	r3, [pc, #180]	; (800136c <HAL_GPIO_Init+0x2d0>)
 80012b6:	689a      	ldr	r2, [r3, #8]
 80012b8:	492c      	ldr	r1, [pc, #176]	; (800136c <HAL_GPIO_Init+0x2d0>)
 80012ba:	69bb      	ldr	r3, [r7, #24]
 80012bc:	4313      	orrs	r3, r2
 80012be:	608b      	str	r3, [r1, #8]
 80012c0:	e006      	b.n	80012d0 <HAL_GPIO_Init+0x234>
        }
        else
        {
          CLEAR_BIT(EXTI->RTSR, iocurrent);
 80012c2:	4b2a      	ldr	r3, [pc, #168]	; (800136c <HAL_GPIO_Init+0x2d0>)
 80012c4:	689a      	ldr	r2, [r3, #8]
 80012c6:	69bb      	ldr	r3, [r7, #24]
 80012c8:	43db      	mvns	r3, r3
 80012ca:	4928      	ldr	r1, [pc, #160]	; (800136c <HAL_GPIO_Init+0x2d0>)
 80012cc:	4013      	ands	r3, r2
 80012ce:	608b      	str	r3, [r1, #8]
        }

        /* Enable or disable the falling trigger */
        if ((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
 80012d0:	683b      	ldr	r3, [r7, #0]
 80012d2:	685b      	ldr	r3, [r3, #4]
 80012d4:	f403 1300 	and.w	r3, r3, #2097152	; 0x200000
 80012d8:	2b00      	cmp	r3, #0
 80012da:	d006      	beq.n	80012ea <HAL_GPIO_Init+0x24e>
        {
          SET_BIT(EXTI->FTSR, iocurrent);
 80012dc:	4b23      	ldr	r3, [pc, #140]	; (800136c <HAL_GPIO_Init+0x2d0>)
 80012de:	68da      	ldr	r2, [r3, #12]
 80012e0:	4922      	ldr	r1, [pc, #136]	; (800136c <HAL_GPIO_Init+0x2d0>)
 80012e2:	69bb      	ldr	r3, [r7, #24]
 80012e4:	4313      	orrs	r3, r2
 80012e6:	60cb      	str	r3, [r1, #12]
 80012e8:	e006      	b.n	80012f8 <HAL_GPIO_Init+0x25c>
        }
        else
        {
          CLEAR_BIT(EXTI->FTSR, iocurrent);
 80012ea:	4b20      	ldr	r3, [pc, #128]	; (800136c <HAL_GPIO_Init+0x2d0>)
 80012ec:	68da      	ldr	r2, [r3, #12]
 80012ee:	69bb      	ldr	r3, [r7, #24]
 80012f0:	43db      	mvns	r3, r3
 80012f2:	491e      	ldr	r1, [pc, #120]	; (800136c <HAL_GPIO_Init+0x2d0>)
 80012f4:	4013      	ands	r3, r2
 80012f6:	60cb      	str	r3, [r1, #12]
        }

        /* Configure the event mask */
        if ((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
 80012f8:	683b      	ldr	r3, [r7, #0]
 80012fa:	685b      	ldr	r3, [r3, #4]
 80012fc:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8001300:	2b00      	cmp	r3, #0
 8001302:	d006      	beq.n	8001312 <HAL_GPIO_Init+0x276>
        {
          SET_BIT(EXTI->EMR, iocurrent);
 8001304:	4b19      	ldr	r3, [pc, #100]	; (800136c <HAL_GPIO_Init+0x2d0>)
 8001306:	685a      	ldr	r2, [r3, #4]
 8001308:	4918      	ldr	r1, [pc, #96]	; (800136c <HAL_GPIO_Init+0x2d0>)
 800130a:	69bb      	ldr	r3, [r7, #24]
 800130c:	4313      	orrs	r3, r2
 800130e:	604b      	str	r3, [r1, #4]
 8001310:	e006      	b.n	8001320 <HAL_GPIO_Init+0x284>
        }
        else
        {
          CLEAR_BIT(EXTI->EMR, iocurrent);
 8001312:	4b16      	ldr	r3, [pc, #88]	; (800136c <HAL_GPIO_Init+0x2d0>)
 8001314:	685a      	ldr	r2, [r3, #4]
 8001316:	69bb      	ldr	r3, [r7, #24]
 8001318:	43db      	mvns	r3, r3
 800131a:	4914      	ldr	r1, [pc, #80]	; (800136c <HAL_GPIO_Init+0x2d0>)
 800131c:	4013      	ands	r3, r2
 800131e:	604b      	str	r3, [r1, #4]
        }

        /* Configure the interrupt mask */
        if ((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
 8001320:	683b      	ldr	r3, [r7, #0]
 8001322:	685b      	ldr	r3, [r3, #4]
 8001324:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 8001328:	2b00      	cmp	r3, #0
 800132a:	d021      	beq.n	8001370 <HAL_GPIO_Init+0x2d4>
        {
          SET_BIT(EXTI->IMR, iocurrent);
 800132c:	4b0f      	ldr	r3, [pc, #60]	; (800136c <HAL_GPIO_Init+0x2d0>)
 800132e:	681a      	ldr	r2, [r3, #0]
 8001330:	490e      	ldr	r1, [pc, #56]	; (800136c <HAL_GPIO_Init+0x2d0>)
 8001332:	69bb      	ldr	r3, [r7, #24]
 8001334:	4313      	orrs	r3, r2
 8001336:	600b      	str	r3, [r1, #0]
 8001338:	e021      	b.n	800137e <HAL_GPIO_Init+0x2e2>
 800133a:	bf00      	nop
 800133c:	10320000 	.word	0x10320000
 8001340:	10310000 	.word	0x10310000
 8001344:	10220000 	.word	0x10220000
 8001348:	10210000 	.word	0x10210000
 800134c:	10120000 	.word	0x10120000
 8001350:	10110000 	.word	0x10110000
 8001354:	40021000 	.word	0x40021000
 8001358:	40010000 	.word	0x40010000
 800135c:	40010800 	.word	0x40010800
 8001360:	40010c00 	.word	0x40010c00
 8001364:	40011000 	.word	0x40011000
 8001368:	40011400 	.word	0x40011400
 800136c:	40010400 	.word	0x40010400
        }
        else
        {
          CLEAR_BIT(EXTI->IMR, iocurrent);
 8001370:	4b0b      	ldr	r3, [pc, #44]	; (80013a0 <HAL_GPIO_Init+0x304>)
 8001372:	681a      	ldr	r2, [r3, #0]
 8001374:	69bb      	ldr	r3, [r7, #24]
 8001376:	43db      	mvns	r3, r3
 8001378:	4909      	ldr	r1, [pc, #36]	; (80013a0 <HAL_GPIO_Init+0x304>)
 800137a:	4013      	ands	r3, r2
 800137c:	600b      	str	r3, [r1, #0]
        }
      }
    }

	position++;
 800137e:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 8001380:	3301      	adds	r3, #1
 8001382:	627b      	str	r3, [r7, #36]	; 0x24
  while (((GPIO_Init->Pin) >> position) != 0x00u)
 8001384:	683b      	ldr	r3, [r7, #0]
 8001386:	681a      	ldr	r2, [r3, #0]
 8001388:	6a7b      	ldr	r3, [r7, #36]	; 0x24
 800138a:	fa22 f303 	lsr.w	r3, r2, r3
 800138e:	2b00      	cmp	r3, #0
 8001390:	f47f ae8e 	bne.w	80010b0 <HAL_GPIO_Init+0x14>
  }
}
 8001394:	bf00      	nop
 8001396:	bf00      	nop
 8001398:	372c      	adds	r7, #44	; 0x2c
 800139a:	46bd      	mov	sp, r7
 800139c:	bc80      	pop	{r7}
 800139e:	4770      	bx	lr
 80013a0:	40010400 	.word	0x40010400

080013a4 <HAL_I2C_Init>:
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
  *                the configuration information for the specified I2C.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
 80013a4:	b580      	push	{r7, lr}
 80013a6:	b084      	sub	sp, #16
 80013a8:	af00      	add	r7, sp, #0
 80013aa:	6078      	str	r0, [r7, #4]
  uint32_t freqrange;
  uint32_t pclk1;

  /* Check the I2C handle allocation */
  if (hi2c == NULL)
 80013ac:	687b      	ldr	r3, [r7, #4]
 80013ae:	2b00      	cmp	r3, #0
 80013b0:	d101      	bne.n	80013b6 <HAL_I2C_Init+0x12>
  {
    return HAL_ERROR;
 80013b2:	2301      	movs	r3, #1
 80013b4:	e12b      	b.n	800160e <HAL_I2C_Init+0x26a>
  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));

  if (hi2c->State == HAL_I2C_STATE_RESET)
 80013b6:	687b      	ldr	r3, [r7, #4]
 80013b8:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
 80013bc:	b2db      	uxtb	r3, r3
 80013be:	2b00      	cmp	r3, #0
 80013c0:	d106      	bne.n	80013d0 <HAL_I2C_Init+0x2c>
  {
    /* Allocate lock resource and initialize it */
    hi2c->Lock = HAL_UNLOCKED;
 80013c2:	687b      	ldr	r3, [r7, #4]
 80013c4:	2200      	movs	r2, #0
 80013c6:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    hi2c->MspInitCallback(hi2c);
#else
    /* Init the low level hardware : GPIO, CLOCK, NVIC */
    HAL_I2C_MspInit(hi2c);
 80013ca:	6878      	ldr	r0, [r7, #4]
 80013cc:	f7ff fc6a 	bl	8000ca4 <HAL_I2C_MspInit>
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
  }

  hi2c->State = HAL_I2C_STATE_BUSY;
 80013d0:	687b      	ldr	r3, [r7, #4]
 80013d2:	2224      	movs	r2, #36	; 0x24
 80013d4:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

  /* Disable the selected I2C peripheral */
  __HAL_I2C_DISABLE(hi2c);
 80013d8:	687b      	ldr	r3, [r7, #4]
 80013da:	681b      	ldr	r3, [r3, #0]
 80013dc:	681a      	ldr	r2, [r3, #0]
 80013de:	687b      	ldr	r3, [r7, #4]
 80013e0:	681b      	ldr	r3, [r3, #0]
 80013e2:	f022 0201 	bic.w	r2, r2, #1
 80013e6:	601a      	str	r2, [r3, #0]

  /*Reset I2C*/
  hi2c->Instance->CR1 |= I2C_CR1_SWRST;
 80013e8:	687b      	ldr	r3, [r7, #4]
 80013ea:	681b      	ldr	r3, [r3, #0]
 80013ec:	681a      	ldr	r2, [r3, #0]
 80013ee:	687b      	ldr	r3, [r7, #4]
 80013f0:	681b      	ldr	r3, [r3, #0]
 80013f2:	f442 4200 	orr.w	r2, r2, #32768	; 0x8000
 80013f6:	601a      	str	r2, [r3, #0]
  hi2c->Instance->CR1 &= ~I2C_CR1_SWRST;
 80013f8:	687b      	ldr	r3, [r7, #4]
 80013fa:	681b      	ldr	r3, [r3, #0]
 80013fc:	681a      	ldr	r2, [r3, #0]
 80013fe:	687b      	ldr	r3, [r7, #4]
 8001400:	681b      	ldr	r3, [r3, #0]
 8001402:	f422 4200 	bic.w	r2, r2, #32768	; 0x8000
 8001406:	601a      	str	r2, [r3, #0]

  /* Get PCLK1 frequency */
  pclk1 = HAL_RCC_GetPCLK1Freq();
 8001408:	f001 f960 	bl	80026cc <HAL_RCC_GetPCLK1Freq>
 800140c:	60f8      	str	r0, [r7, #12]

  /* Check the minimum allowed PCLK1 frequency */
  if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U)
 800140e:	687b      	ldr	r3, [r7, #4]
 8001410:	685b      	ldr	r3, [r3, #4]
 8001412:	4a81      	ldr	r2, [pc, #516]	; (8001618 <HAL_I2C_Init+0x274>)
 8001414:	4293      	cmp	r3, r2
 8001416:	d807      	bhi.n	8001428 <HAL_I2C_Init+0x84>
 8001418:	68fb      	ldr	r3, [r7, #12]
 800141a:	4a80      	ldr	r2, [pc, #512]	; (800161c <HAL_I2C_Init+0x278>)
 800141c:	4293      	cmp	r3, r2
 800141e:	bf94      	ite	ls
 8001420:	2301      	movls	r3, #1
 8001422:	2300      	movhi	r3, #0
 8001424:	b2db      	uxtb	r3, r3
 8001426:	e006      	b.n	8001436 <HAL_I2C_Init+0x92>
 8001428:	68fb      	ldr	r3, [r7, #12]
 800142a:	4a7d      	ldr	r2, [pc, #500]	; (8001620 <HAL_I2C_Init+0x27c>)
 800142c:	4293      	cmp	r3, r2
 800142e:	bf94      	ite	ls
 8001430:	2301      	movls	r3, #1
 8001432:	2300      	movhi	r3, #0
 8001434:	b2db      	uxtb	r3, r3
 8001436:	2b00      	cmp	r3, #0
 8001438:	d001      	beq.n	800143e <HAL_I2C_Init+0x9a>
  {
    return HAL_ERROR;
 800143a:	2301      	movs	r3, #1
 800143c:	e0e7      	b.n	800160e <HAL_I2C_Init+0x26a>
  }

  /* Calculate frequency range */
  freqrange = I2C_FREQRANGE(pclk1);
 800143e:	68fb      	ldr	r3, [r7, #12]
 8001440:	4a78      	ldr	r2, [pc, #480]	; (8001624 <HAL_I2C_Init+0x280>)
 8001442:	fba2 2303 	umull	r2, r3, r2, r3
 8001446:	0c9b      	lsrs	r3, r3, #18
 8001448:	60bb      	str	r3, [r7, #8]

  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
  /* Configure I2Cx: Frequency range */
  MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
 800144a:	687b      	ldr	r3, [r7, #4]
 800144c:	681b      	ldr	r3, [r3, #0]
 800144e:	685b      	ldr	r3, [r3, #4]
 8001450:	f023 013f 	bic.w	r1, r3, #63	; 0x3f
 8001454:	687b      	ldr	r3, [r7, #4]
 8001456:	681b      	ldr	r3, [r3, #0]
 8001458:	68ba      	ldr	r2, [r7, #8]
 800145a:	430a      	orrs	r2, r1
 800145c:	605a      	str	r2, [r3, #4]

  /*---------------------------- I2Cx TRISE Configuration --------------------*/
  /* Configure I2Cx: Rise Time */
  MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
 800145e:	687b      	ldr	r3, [r7, #4]
 8001460:	681b      	ldr	r3, [r3, #0]
 8001462:	6a1b      	ldr	r3, [r3, #32]
 8001464:	f023 013f 	bic.w	r1, r3, #63	; 0x3f
 8001468:	687b      	ldr	r3, [r7, #4]
 800146a:	685b      	ldr	r3, [r3, #4]
 800146c:	4a6a      	ldr	r2, [pc, #424]	; (8001618 <HAL_I2C_Init+0x274>)
 800146e:	4293      	cmp	r3, r2
 8001470:	d802      	bhi.n	8001478 <HAL_I2C_Init+0xd4>
 8001472:	68bb      	ldr	r3, [r7, #8]
 8001474:	3301      	adds	r3, #1
 8001476:	e009      	b.n	800148c <HAL_I2C_Init+0xe8>
 8001478:	68bb      	ldr	r3, [r7, #8]
 800147a:	f44f 7296 	mov.w	r2, #300	; 0x12c
 800147e:	fb02 f303 	mul.w	r3, r2, r3
 8001482:	4a69      	ldr	r2, [pc, #420]	; (8001628 <HAL_I2C_Init+0x284>)
 8001484:	fba2 2303 	umull	r2, r3, r2, r3
 8001488:	099b      	lsrs	r3, r3, #6
 800148a:	3301      	adds	r3, #1
 800148c:	687a      	ldr	r2, [r7, #4]
 800148e:	6812      	ldr	r2, [r2, #0]
 8001490:	430b      	orrs	r3, r1
 8001492:	6213      	str	r3, [r2, #32]

  /*---------------------------- I2Cx CCR Configuration ----------------------*/
  /* Configure I2Cx: Speed */
  MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
 8001494:	687b      	ldr	r3, [r7, #4]
 8001496:	681b      	ldr	r3, [r3, #0]
 8001498:	69db      	ldr	r3, [r3, #28]
 800149a:	f423 424f 	bic.w	r2, r3, #52992	; 0xcf00
 800149e:	f022 02ff 	bic.w	r2, r2, #255	; 0xff
 80014a2:	687b      	ldr	r3, [r7, #4]
 80014a4:	685b      	ldr	r3, [r3, #4]
 80014a6:	495c      	ldr	r1, [pc, #368]	; (8001618 <HAL_I2C_Init+0x274>)
 80014a8:	428b      	cmp	r3, r1
 80014aa:	d819      	bhi.n	80014e0 <HAL_I2C_Init+0x13c>
 80014ac:	68fb      	ldr	r3, [r7, #12]
 80014ae:	1e59      	subs	r1, r3, #1
 80014b0:	687b      	ldr	r3, [r7, #4]
 80014b2:	685b      	ldr	r3, [r3, #4]
 80014b4:	005b      	lsls	r3, r3, #1
 80014b6:	fbb1 f3f3 	udiv	r3, r1, r3
 80014ba:	1c59      	adds	r1, r3, #1
 80014bc:	f640 73fc 	movw	r3, #4092	; 0xffc
 80014c0:	400b      	ands	r3, r1
 80014c2:	2b00      	cmp	r3, #0
 80014c4:	d00a      	beq.n	80014dc <HAL_I2C_Init+0x138>
 80014c6:	68fb      	ldr	r3, [r7, #12]
 80014c8:	1e59      	subs	r1, r3, #1
 80014ca:	687b      	ldr	r3, [r7, #4]
 80014cc:	685b      	ldr	r3, [r3, #4]
 80014ce:	005b      	lsls	r3, r3, #1
 80014d0:	fbb1 f3f3 	udiv	r3, r1, r3
 80014d4:	3301      	adds	r3, #1
 80014d6:	f3c3 030b 	ubfx	r3, r3, #0, #12
 80014da:	e051      	b.n	8001580 <HAL_I2C_Init+0x1dc>
 80014dc:	2304      	movs	r3, #4
 80014de:	e04f      	b.n	8001580 <HAL_I2C_Init+0x1dc>
 80014e0:	687b      	ldr	r3, [r7, #4]
 80014e2:	689b      	ldr	r3, [r3, #8]
 80014e4:	2b00      	cmp	r3, #0
 80014e6:	d111      	bne.n	800150c <HAL_I2C_Init+0x168>
 80014e8:	68fb      	ldr	r3, [r7, #12]
 80014ea:	1e58      	subs	r0, r3, #1
 80014ec:	687b      	ldr	r3, [r7, #4]
 80014ee:	6859      	ldr	r1, [r3, #4]
 80014f0:	460b      	mov	r3, r1
 80014f2:	005b      	lsls	r3, r3, #1
 80014f4:	440b      	add	r3, r1
 80014f6:	fbb0 f3f3 	udiv	r3, r0, r3
 80014fa:	3301      	adds	r3, #1
 80014fc:	f3c3 030b 	ubfx	r3, r3, #0, #12
 8001500:	2b00      	cmp	r3, #0
 8001502:	bf0c      	ite	eq
 8001504:	2301      	moveq	r3, #1
 8001506:	2300      	movne	r3, #0
 8001508:	b2db      	uxtb	r3, r3
 800150a:	e012      	b.n	8001532 <HAL_I2C_Init+0x18e>
 800150c:	68fb      	ldr	r3, [r7, #12]
 800150e:	1e58      	subs	r0, r3, #1
 8001510:	687b      	ldr	r3, [r7, #4]
 8001512:	6859      	ldr	r1, [r3, #4]
 8001514:	460b      	mov	r3, r1
 8001516:	009b      	lsls	r3, r3, #2
 8001518:	440b      	add	r3, r1
 800151a:	0099      	lsls	r1, r3, #2
 800151c:	440b      	add	r3, r1
 800151e:	fbb0 f3f3 	udiv	r3, r0, r3
 8001522:	3301      	adds	r3, #1
 8001524:	f3c3 030b 	ubfx	r3, r3, #0, #12
 8001528:	2b00      	cmp	r3, #0
 800152a:	bf0c      	ite	eq
 800152c:	2301      	moveq	r3, #1
 800152e:	2300      	movne	r3, #0
 8001530:	b2db      	uxtb	r3, r3
 8001532:	2b00      	cmp	r3, #0
 8001534:	d001      	beq.n	800153a <HAL_I2C_Init+0x196>
 8001536:	2301      	movs	r3, #1
 8001538:	e022      	b.n	8001580 <HAL_I2C_Init+0x1dc>
 800153a:	687b      	ldr	r3, [r7, #4]
 800153c:	689b      	ldr	r3, [r3, #8]
 800153e:	2b00      	cmp	r3, #0
 8001540:	d10e      	bne.n	8001560 <HAL_I2C_Init+0x1bc>
 8001542:	68fb      	ldr	r3, [r7, #12]
 8001544:	1e58      	subs	r0, r3, #1
 8001546:	687b      	ldr	r3, [r7, #4]
 8001548:	6859      	ldr	r1, [r3, #4]
 800154a:	460b      	mov	r3, r1
 800154c:	005b      	lsls	r3, r3, #1
 800154e:	440b      	add	r3, r1
 8001550:	fbb0 f3f3 	udiv	r3, r0, r3
 8001554:	3301      	adds	r3, #1
 8001556:	f3c3 030b 	ubfx	r3, r3, #0, #12
 800155a:	f443 4300 	orr.w	r3, r3, #32768	; 0x8000
 800155e:	e00f      	b.n	8001580 <HAL_I2C_Init+0x1dc>
 8001560:	68fb      	ldr	r3, [r7, #12]
 8001562:	1e58      	subs	r0, r3, #1
 8001564:	687b      	ldr	r3, [r7, #4]
 8001566:	6859      	ldr	r1, [r3, #4]
 8001568:	460b      	mov	r3, r1
 800156a:	009b      	lsls	r3, r3, #2
 800156c:	440b      	add	r3, r1
 800156e:	0099      	lsls	r1, r3, #2
 8001570:	440b      	add	r3, r1
 8001572:	fbb0 f3f3 	udiv	r3, r0, r3
 8001576:	3301      	adds	r3, #1
 8001578:	f3c3 030b 	ubfx	r3, r3, #0, #12
 800157c:	f443 4340 	orr.w	r3, r3, #49152	; 0xc000
 8001580:	6879      	ldr	r1, [r7, #4]
 8001582:	6809      	ldr	r1, [r1, #0]
 8001584:	4313      	orrs	r3, r2
 8001586:	61cb      	str	r3, [r1, #28]

  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
  /* Configure I2Cx: Generalcall and NoStretch mode */
  MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
 8001588:	687b      	ldr	r3, [r7, #4]
 800158a:	681b      	ldr	r3, [r3, #0]
 800158c:	681b      	ldr	r3, [r3, #0]
 800158e:	f023 01c0 	bic.w	r1, r3, #192	; 0xc0
 8001592:	687b      	ldr	r3, [r7, #4]
 8001594:	69da      	ldr	r2, [r3, #28]
 8001596:	687b      	ldr	r3, [r7, #4]
 8001598:	6a1b      	ldr	r3, [r3, #32]
 800159a:	431a      	orrs	r2, r3
 800159c:	687b      	ldr	r3, [r7, #4]
 800159e:	681b      	ldr	r3, [r3, #0]
 80015a0:	430a      	orrs	r2, r1
 80015a2:	601a      	str	r2, [r3, #0]

  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
  /* Configure I2Cx: Own Address1 and addressing mode */
  MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
 80015a4:	687b      	ldr	r3, [r7, #4]
 80015a6:	681b      	ldr	r3, [r3, #0]
 80015a8:	689b      	ldr	r3, [r3, #8]
 80015aa:	f423 4303 	bic.w	r3, r3, #33536	; 0x8300
 80015ae:	f023 03ff 	bic.w	r3, r3, #255	; 0xff
 80015b2:	687a      	ldr	r2, [r7, #4]
 80015b4:	6911      	ldr	r1, [r2, #16]
 80015b6:	687a      	ldr	r2, [r7, #4]
 80015b8:	68d2      	ldr	r2, [r2, #12]
 80015ba:	4311      	orrs	r1, r2
 80015bc:	687a      	ldr	r2, [r7, #4]
 80015be:	6812      	ldr	r2, [r2, #0]
 80015c0:	430b      	orrs	r3, r1
 80015c2:	6093      	str	r3, [r2, #8]

  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
  /* Configure I2Cx: Dual mode and Own Address2 */
  MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
 80015c4:	687b      	ldr	r3, [r7, #4]
 80015c6:	681b      	ldr	r3, [r3, #0]
 80015c8:	68db      	ldr	r3, [r3, #12]
 80015ca:	f023 01ff 	bic.w	r1, r3, #255	; 0xff
 80015ce:	687b      	ldr	r3, [r7, #4]
 80015d0:	695a      	ldr	r2, [r3, #20]
 80015d2:	687b      	ldr	r3, [r7, #4]
 80015d4:	699b      	ldr	r3, [r3, #24]
 80015d6:	431a      	orrs	r2, r3
 80015d8:	687b      	ldr	r3, [r7, #4]
 80015da:	681b      	ldr	r3, [r3, #0]
 80015dc:	430a      	orrs	r2, r1
 80015de:	60da      	str	r2, [r3, #12]

  /* Enable the selected I2C peripheral */
  __HAL_I2C_ENABLE(hi2c);
 80015e0:	687b      	ldr	r3, [r7, #4]
 80015e2:	681b      	ldr	r3, [r3, #0]
 80015e4:	681a      	ldr	r2, [r3, #0]
 80015e6:	687b      	ldr	r3, [r7, #4]
 80015e8:	681b      	ldr	r3, [r3, #0]
 80015ea:	f042 0201 	orr.w	r2, r2, #1
 80015ee:	601a      	str	r2, [r3, #0]

  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 80015f0:	687b      	ldr	r3, [r7, #4]
 80015f2:	2200      	movs	r2, #0
 80015f4:	641a      	str	r2, [r3, #64]	; 0x40
  hi2c->State = HAL_I2C_STATE_READY;
 80015f6:	687b      	ldr	r3, [r7, #4]
 80015f8:	2220      	movs	r2, #32
 80015fa:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
  hi2c->PreviousState = I2C_STATE_NONE;
 80015fe:	687b      	ldr	r3, [r7, #4]
 8001600:	2200      	movs	r2, #0
 8001602:	631a      	str	r2, [r3, #48]	; 0x30
  hi2c->Mode = HAL_I2C_MODE_NONE;
 8001604:	687b      	ldr	r3, [r7, #4]
 8001606:	2200      	movs	r2, #0
 8001608:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e

  return HAL_OK;
 800160c:	2300      	movs	r3, #0
}
 800160e:	4618      	mov	r0, r3
 8001610:	3710      	adds	r7, #16
 8001612:	46bd      	mov	sp, r7
 8001614:	bd80      	pop	{r7, pc}
 8001616:	bf00      	nop
 8001618:	000186a0 	.word	0x000186a0
 800161c:	001e847f 	.word	0x001e847f
 8001620:	003d08ff 	.word	0x003d08ff
 8001624:	431bde83 	.word	0x431bde83
 8001628:	10624dd3 	.word	0x10624dd3

0800162c <HAL_I2C_Master_Transmit>:
  * @param  Size Amount of data to be sent
  * @param  Timeout Timeout duration
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
 800162c:	b580      	push	{r7, lr}
 800162e:	b088      	sub	sp, #32
 8001630:	af02      	add	r7, sp, #8
 8001632:	60f8      	str	r0, [r7, #12]
 8001634:	607a      	str	r2, [r7, #4]
 8001636:	461a      	mov	r2, r3
 8001638:	460b      	mov	r3, r1
 800163a:	817b      	strh	r3, [r7, #10]
 800163c:	4613      	mov	r3, r2
 800163e:	813b      	strh	r3, [r7, #8]
  /* Init tickstart for timeout management*/
  uint32_t tickstart = HAL_GetTick();
 8001640:	f7ff fc1a 	bl	8000e78 <HAL_GetTick>
 8001644:	6178      	str	r0, [r7, #20]

  if (hi2c->State == HAL_I2C_STATE_READY)
 8001646:	68fb      	ldr	r3, [r7, #12]
 8001648:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
 800164c:	b2db      	uxtb	r3, r3
 800164e:	2b20      	cmp	r3, #32
 8001650:	f040 80e0 	bne.w	8001814 <HAL_I2C_Master_Transmit+0x1e8>
  {
    /* Wait until BUSY flag is reset */
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
 8001654:	697b      	ldr	r3, [r7, #20]
 8001656:	9300      	str	r3, [sp, #0]
 8001658:	2319      	movs	r3, #25
 800165a:	2201      	movs	r2, #1
 800165c:	4970      	ldr	r1, [pc, #448]	; (8001820 <HAL_I2C_Master_Transmit+0x1f4>)
 800165e:	68f8      	ldr	r0, [r7, #12]
 8001660:	f000 fa92 	bl	8001b88 <I2C_WaitOnFlagUntilTimeout>
 8001664:	4603      	mov	r3, r0
 8001666:	2b00      	cmp	r3, #0
 8001668:	d001      	beq.n	800166e <HAL_I2C_Master_Transmit+0x42>
    {
      return HAL_BUSY;
 800166a:	2302      	movs	r3, #2
 800166c:	e0d3      	b.n	8001816 <HAL_I2C_Master_Transmit+0x1ea>
    }

    /* Process Locked */
    __HAL_LOCK(hi2c);
 800166e:	68fb      	ldr	r3, [r7, #12]
 8001670:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
 8001674:	2b01      	cmp	r3, #1
 8001676:	d101      	bne.n	800167c <HAL_I2C_Master_Transmit+0x50>
 8001678:	2302      	movs	r3, #2
 800167a:	e0cc      	b.n	8001816 <HAL_I2C_Master_Transmit+0x1ea>
 800167c:	68fb      	ldr	r3, [r7, #12]
 800167e:	2201      	movs	r2, #1
 8001680:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
 8001684:	68fb      	ldr	r3, [r7, #12]
 8001686:	681b      	ldr	r3, [r3, #0]
 8001688:	681b      	ldr	r3, [r3, #0]
 800168a:	f003 0301 	and.w	r3, r3, #1
 800168e:	2b01      	cmp	r3, #1
 8001690:	d007      	beq.n	80016a2 <HAL_I2C_Master_Transmit+0x76>
    {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
 8001692:	68fb      	ldr	r3, [r7, #12]
 8001694:	681b      	ldr	r3, [r3, #0]
 8001696:	681a      	ldr	r2, [r3, #0]
 8001698:	68fb      	ldr	r3, [r7, #12]
 800169a:	681b      	ldr	r3, [r3, #0]
 800169c:	f042 0201 	orr.w	r2, r2, #1
 80016a0:	601a      	str	r2, [r3, #0]
    }

    /* Disable Pos */
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 80016a2:	68fb      	ldr	r3, [r7, #12]
 80016a4:	681b      	ldr	r3, [r3, #0]
 80016a6:	681a      	ldr	r2, [r3, #0]
 80016a8:	68fb      	ldr	r3, [r7, #12]
 80016aa:	681b      	ldr	r3, [r3, #0]
 80016ac:	f422 6200 	bic.w	r2, r2, #2048	; 0x800
 80016b0:	601a      	str	r2, [r3, #0]

    hi2c->State       = HAL_I2C_STATE_BUSY_TX;
 80016b2:	68fb      	ldr	r3, [r7, #12]
 80016b4:	2221      	movs	r2, #33	; 0x21
 80016b6:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
    hi2c->Mode        = HAL_I2C_MODE_MASTER;
 80016ba:	68fb      	ldr	r3, [r7, #12]
 80016bc:	2210      	movs	r2, #16
 80016be:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
    hi2c->ErrorCode   = HAL_I2C_ERROR_NONE;
 80016c2:	68fb      	ldr	r3, [r7, #12]
 80016c4:	2200      	movs	r2, #0
 80016c6:	641a      	str	r2, [r3, #64]	; 0x40

    /* Prepare transfer parameters */
    hi2c->pBuffPtr    = pData;
 80016c8:	68fb      	ldr	r3, [r7, #12]
 80016ca:	687a      	ldr	r2, [r7, #4]
 80016cc:	625a      	str	r2, [r3, #36]	; 0x24
    hi2c->XferCount   = Size;
 80016ce:	68fb      	ldr	r3, [r7, #12]
 80016d0:	893a      	ldrh	r2, [r7, #8]
 80016d2:	855a      	strh	r2, [r3, #42]	; 0x2a
    hi2c->XferSize    = hi2c->XferCount;
 80016d4:	68fb      	ldr	r3, [r7, #12]
 80016d6:	8d5b      	ldrh	r3, [r3, #42]	; 0x2a
 80016d8:	b29a      	uxth	r2, r3
 80016da:	68fb      	ldr	r3, [r7, #12]
 80016dc:	851a      	strh	r2, [r3, #40]	; 0x28
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
 80016de:	68fb      	ldr	r3, [r7, #12]
 80016e0:	4a50      	ldr	r2, [pc, #320]	; (8001824 <HAL_I2C_Master_Transmit+0x1f8>)
 80016e2:	62da      	str	r2, [r3, #44]	; 0x2c

    /* Send Slave Address */
    if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK)
 80016e4:	8979      	ldrh	r1, [r7, #10]
 80016e6:	697b      	ldr	r3, [r7, #20]
 80016e8:	6a3a      	ldr	r2, [r7, #32]
 80016ea:	68f8      	ldr	r0, [r7, #12]
 80016ec:	f000 f9ca 	bl	8001a84 <I2C_MasterRequestWrite>
 80016f0:	4603      	mov	r3, r0
 80016f2:	2b00      	cmp	r3, #0
 80016f4:	d001      	beq.n	80016fa <HAL_I2C_Master_Transmit+0xce>
    {
      return HAL_ERROR;
 80016f6:	2301      	movs	r3, #1
 80016f8:	e08d      	b.n	8001816 <HAL_I2C_Master_Transmit+0x1ea>
    }

    /* Clear ADDR flag */
    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 80016fa:	2300      	movs	r3, #0
 80016fc:	613b      	str	r3, [r7, #16]
 80016fe:	68fb      	ldr	r3, [r7, #12]
 8001700:	681b      	ldr	r3, [r3, #0]
 8001702:	695b      	ldr	r3, [r3, #20]
 8001704:	613b      	str	r3, [r7, #16]
 8001706:	68fb      	ldr	r3, [r7, #12]
 8001708:	681b      	ldr	r3, [r3, #0]
 800170a:	699b      	ldr	r3, [r3, #24]
 800170c:	613b      	str	r3, [r7, #16]
 800170e:	693b      	ldr	r3, [r7, #16]

    while (hi2c->XferSize > 0U)
 8001710:	e066      	b.n	80017e0 <HAL_I2C_Master_Transmit+0x1b4>
    {
      /* Wait until TXE flag is set */
      if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
 8001712:	697a      	ldr	r2, [r7, #20]
 8001714:	6a39      	ldr	r1, [r7, #32]
 8001716:	68f8      	ldr	r0, [r7, #12]
 8001718:	f000 fb50 	bl	8001dbc <I2C_WaitOnTXEFlagUntilTimeout>
 800171c:	4603      	mov	r3, r0
 800171e:	2b00      	cmp	r3, #0
 8001720:	d00d      	beq.n	800173e <HAL_I2C_Master_Transmit+0x112>
      {
        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
 8001722:	68fb      	ldr	r3, [r7, #12]
 8001724:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001726:	2b04      	cmp	r3, #4
 8001728:	d107      	bne.n	800173a <HAL_I2C_Master_Transmit+0x10e>
        {
          /* Generate Stop */
          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 800172a:	68fb      	ldr	r3, [r7, #12]
 800172c:	681b      	ldr	r3, [r3, #0]
 800172e:	681a      	ldr	r2, [r3, #0]
 8001730:	68fb      	ldr	r3, [r7, #12]
 8001732:	681b      	ldr	r3, [r3, #0]
 8001734:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 8001738:	601a      	str	r2, [r3, #0]
        }
        return HAL_ERROR;
 800173a:	2301      	movs	r3, #1
 800173c:	e06b      	b.n	8001816 <HAL_I2C_Master_Transmit+0x1ea>
      }

      /* Write data to DR */
      hi2c->Instance->DR = *hi2c->pBuffPtr;
 800173e:	68fb      	ldr	r3, [r7, #12]
 8001740:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001742:	781a      	ldrb	r2, [r3, #0]
 8001744:	68fb      	ldr	r3, [r7, #12]
 8001746:	681b      	ldr	r3, [r3, #0]
 8001748:	611a      	str	r2, [r3, #16]

      /* Increment Buffer pointer */
      hi2c->pBuffPtr++;
 800174a:	68fb      	ldr	r3, [r7, #12]
 800174c:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 800174e:	1c5a      	adds	r2, r3, #1
 8001750:	68fb      	ldr	r3, [r7, #12]
 8001752:	625a      	str	r2, [r3, #36]	; 0x24

      /* Update counter */
      hi2c->XferCount--;
 8001754:	68fb      	ldr	r3, [r7, #12]
 8001756:	8d5b      	ldrh	r3, [r3, #42]	; 0x2a
 8001758:	b29b      	uxth	r3, r3
 800175a:	3b01      	subs	r3, #1
 800175c:	b29a      	uxth	r2, r3
 800175e:	68fb      	ldr	r3, [r7, #12]
 8001760:	855a      	strh	r2, [r3, #42]	; 0x2a
      hi2c->XferSize--;
 8001762:	68fb      	ldr	r3, [r7, #12]
 8001764:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
 8001766:	3b01      	subs	r3, #1
 8001768:	b29a      	uxth	r2, r3
 800176a:	68fb      	ldr	r3, [r7, #12]
 800176c:	851a      	strh	r2, [r3, #40]	; 0x28

      if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U))
 800176e:	68fb      	ldr	r3, [r7, #12]
 8001770:	681b      	ldr	r3, [r3, #0]
 8001772:	695b      	ldr	r3, [r3, #20]
 8001774:	f003 0304 	and.w	r3, r3, #4
 8001778:	2b04      	cmp	r3, #4
 800177a:	d11b      	bne.n	80017b4 <HAL_I2C_Master_Transmit+0x188>
 800177c:	68fb      	ldr	r3, [r7, #12]
 800177e:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
 8001780:	2b00      	cmp	r3, #0
 8001782:	d017      	beq.n	80017b4 <HAL_I2C_Master_Transmit+0x188>
      {
        /* Write data to DR */
        hi2c->Instance->DR = *hi2c->pBuffPtr;
 8001784:	68fb      	ldr	r3, [r7, #12]
 8001786:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001788:	781a      	ldrb	r2, [r3, #0]
 800178a:	68fb      	ldr	r3, [r7, #12]
 800178c:	681b      	ldr	r3, [r3, #0]
 800178e:	611a      	str	r2, [r3, #16]

        /* Increment Buffer pointer */
        hi2c->pBuffPtr++;
 8001790:	68fb      	ldr	r3, [r7, #12]
 8001792:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8001794:	1c5a      	adds	r2, r3, #1
 8001796:	68fb      	ldr	r3, [r7, #12]
 8001798:	625a      	str	r2, [r3, #36]	; 0x24

        /* Update counter */
        hi2c->XferCount--;
 800179a:	68fb      	ldr	r3, [r7, #12]
 800179c:	8d5b      	ldrh	r3, [r3, #42]	; 0x2a
 800179e:	b29b      	uxth	r3, r3
 80017a0:	3b01      	subs	r3, #1
 80017a2:	b29a      	uxth	r2, r3
 80017a4:	68fb      	ldr	r3, [r7, #12]
 80017a6:	855a      	strh	r2, [r3, #42]	; 0x2a
        hi2c->XferSize--;
 80017a8:	68fb      	ldr	r3, [r7, #12]
 80017aa:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
 80017ac:	3b01      	subs	r3, #1
 80017ae:	b29a      	uxth	r2, r3
 80017b0:	68fb      	ldr	r3, [r7, #12]
 80017b2:	851a      	strh	r2, [r3, #40]	; 0x28
      }

      /* Wait until BTF flag is set */
      if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
 80017b4:	697a      	ldr	r2, [r7, #20]
 80017b6:	6a39      	ldr	r1, [r7, #32]
 80017b8:	68f8      	ldr	r0, [r7, #12]
 80017ba:	f000 fb47 	bl	8001e4c <I2C_WaitOnBTFFlagUntilTimeout>
 80017be:	4603      	mov	r3, r0
 80017c0:	2b00      	cmp	r3, #0
 80017c2:	d00d      	beq.n	80017e0 <HAL_I2C_Master_Transmit+0x1b4>
      {
        if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
 80017c4:	68fb      	ldr	r3, [r7, #12]
 80017c6:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 80017c8:	2b04      	cmp	r3, #4
 80017ca:	d107      	bne.n	80017dc <HAL_I2C_Master_Transmit+0x1b0>
        {
          /* Generate Stop */
          SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 80017cc:	68fb      	ldr	r3, [r7, #12]
 80017ce:	681b      	ldr	r3, [r3, #0]
 80017d0:	681a      	ldr	r2, [r3, #0]
 80017d2:	68fb      	ldr	r3, [r7, #12]
 80017d4:	681b      	ldr	r3, [r3, #0]
 80017d6:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 80017da:	601a      	str	r2, [r3, #0]
        }
        return HAL_ERROR;
 80017dc:	2301      	movs	r3, #1
 80017de:	e01a      	b.n	8001816 <HAL_I2C_Master_Transmit+0x1ea>
    while (hi2c->XferSize > 0U)
 80017e0:	68fb      	ldr	r3, [r7, #12]
 80017e2:	8d1b      	ldrh	r3, [r3, #40]	; 0x28
 80017e4:	2b00      	cmp	r3, #0
 80017e6:	d194      	bne.n	8001712 <HAL_I2C_Master_Transmit+0xe6>
      }
    }

    /* Generate Stop */
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 80017e8:	68fb      	ldr	r3, [r7, #12]
 80017ea:	681b      	ldr	r3, [r3, #0]
 80017ec:	681a      	ldr	r2, [r3, #0]
 80017ee:	68fb      	ldr	r3, [r7, #12]
 80017f0:	681b      	ldr	r3, [r3, #0]
 80017f2:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 80017f6:	601a      	str	r2, [r3, #0]

    hi2c->State = HAL_I2C_STATE_READY;
 80017f8:	68fb      	ldr	r3, [r7, #12]
 80017fa:	2220      	movs	r2, #32
 80017fc:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
    hi2c->Mode = HAL_I2C_MODE_NONE;
 8001800:	68fb      	ldr	r3, [r7, #12]
 8001802:	2200      	movs	r2, #0
 8001804:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);
 8001808:	68fb      	ldr	r3, [r7, #12]
 800180a:	2200      	movs	r2, #0
 800180c:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    return HAL_OK;
 8001810:	2300      	movs	r3, #0
 8001812:	e000      	b.n	8001816 <HAL_I2C_Master_Transmit+0x1ea>
  }
  else
  {
    return HAL_BUSY;
 8001814:	2302      	movs	r3, #2
  }
}
 8001816:	4618      	mov	r0, r3
 8001818:	3718      	adds	r7, #24
 800181a:	46bd      	mov	sp, r7
 800181c:	bd80      	pop	{r7, pc}
 800181e:	bf00      	nop
 8001820:	00100002 	.word	0x00100002
 8001824:	ffff0000 	.word	0xffff0000

08001828 <HAL_I2C_IsDeviceReady>:
  * @param  Trials Number of trials
  * @param  Timeout Timeout duration
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
{
 8001828:	b580      	push	{r7, lr}
 800182a:	b08a      	sub	sp, #40	; 0x28
 800182c:	af02      	add	r7, sp, #8
 800182e:	60f8      	str	r0, [r7, #12]
 8001830:	607a      	str	r2, [r7, #4]
 8001832:	603b      	str	r3, [r7, #0]
 8001834:	460b      	mov	r3, r1
 8001836:	817b      	strh	r3, [r7, #10]
  /* Get tick */
  uint32_t tickstart = HAL_GetTick();
 8001838:	f7ff fb1e 	bl	8000e78 <HAL_GetTick>
 800183c:	61f8      	str	r0, [r7, #28]
  uint32_t I2C_Trials = 0U;
 800183e:	2300      	movs	r3, #0
 8001840:	61bb      	str	r3, [r7, #24]
  FlagStatus tmp1;
  FlagStatus tmp2;

  if (hi2c->State == HAL_I2C_STATE_READY)
 8001842:	68fb      	ldr	r3, [r7, #12]
 8001844:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
 8001848:	b2db      	uxtb	r3, r3
 800184a:	2b20      	cmp	r3, #32
 800184c:	f040 8111 	bne.w	8001a72 <HAL_I2C_IsDeviceReady+0x24a>
  {
    /* Wait until BUSY flag is reset */
    if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
 8001850:	69fb      	ldr	r3, [r7, #28]
 8001852:	9300      	str	r3, [sp, #0]
 8001854:	2319      	movs	r3, #25
 8001856:	2201      	movs	r2, #1
 8001858:	4988      	ldr	r1, [pc, #544]	; (8001a7c <HAL_I2C_IsDeviceReady+0x254>)
 800185a:	68f8      	ldr	r0, [r7, #12]
 800185c:	f000 f994 	bl	8001b88 <I2C_WaitOnFlagUntilTimeout>
 8001860:	4603      	mov	r3, r0
 8001862:	2b00      	cmp	r3, #0
 8001864:	d001      	beq.n	800186a <HAL_I2C_IsDeviceReady+0x42>
    {
      return HAL_BUSY;
 8001866:	2302      	movs	r3, #2
 8001868:	e104      	b.n	8001a74 <HAL_I2C_IsDeviceReady+0x24c>
    }

    /* Process Locked */
    __HAL_LOCK(hi2c);
 800186a:	68fb      	ldr	r3, [r7, #12]
 800186c:	f893 303c 	ldrb.w	r3, [r3, #60]	; 0x3c
 8001870:	2b01      	cmp	r3, #1
 8001872:	d101      	bne.n	8001878 <HAL_I2C_IsDeviceReady+0x50>
 8001874:	2302      	movs	r3, #2
 8001876:	e0fd      	b.n	8001a74 <HAL_I2C_IsDeviceReady+0x24c>
 8001878:	68fb      	ldr	r3, [r7, #12]
 800187a:	2201      	movs	r2, #1
 800187c:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    /* Check if the I2C is already enabled */
    if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE)
 8001880:	68fb      	ldr	r3, [r7, #12]
 8001882:	681b      	ldr	r3, [r3, #0]
 8001884:	681b      	ldr	r3, [r3, #0]
 8001886:	f003 0301 	and.w	r3, r3, #1
 800188a:	2b01      	cmp	r3, #1
 800188c:	d007      	beq.n	800189e <HAL_I2C_IsDeviceReady+0x76>
    {
      /* Enable I2C peripheral */
      __HAL_I2C_ENABLE(hi2c);
 800188e:	68fb      	ldr	r3, [r7, #12]
 8001890:	681b      	ldr	r3, [r3, #0]
 8001892:	681a      	ldr	r2, [r3, #0]
 8001894:	68fb      	ldr	r3, [r7, #12]
 8001896:	681b      	ldr	r3, [r3, #0]
 8001898:	f042 0201 	orr.w	r2, r2, #1
 800189c:	601a      	str	r2, [r3, #0]
    }

    /* Disable Pos */
    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
 800189e:	68fb      	ldr	r3, [r7, #12]
 80018a0:	681b      	ldr	r3, [r3, #0]
 80018a2:	681a      	ldr	r2, [r3, #0]
 80018a4:	68fb      	ldr	r3, [r7, #12]
 80018a6:	681b      	ldr	r3, [r3, #0]
 80018a8:	f422 6200 	bic.w	r2, r2, #2048	; 0x800
 80018ac:	601a      	str	r2, [r3, #0]

    hi2c->State = HAL_I2C_STATE_BUSY;
 80018ae:	68fb      	ldr	r3, [r7, #12]
 80018b0:	2224      	movs	r2, #36	; 0x24
 80018b2:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
 80018b6:	68fb      	ldr	r3, [r7, #12]
 80018b8:	2200      	movs	r2, #0
 80018ba:	641a      	str	r2, [r3, #64]	; 0x40
    hi2c->XferOptions = I2C_NO_OPTION_FRAME;
 80018bc:	68fb      	ldr	r3, [r7, #12]
 80018be:	4a70      	ldr	r2, [pc, #448]	; (8001a80 <HAL_I2C_IsDeviceReady+0x258>)
 80018c0:	62da      	str	r2, [r3, #44]	; 0x2c

    do
    {
      /* Generate Start */
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
 80018c2:	68fb      	ldr	r3, [r7, #12]
 80018c4:	681b      	ldr	r3, [r3, #0]
 80018c6:	681a      	ldr	r2, [r3, #0]
 80018c8:	68fb      	ldr	r3, [r7, #12]
 80018ca:	681b      	ldr	r3, [r3, #0]
 80018cc:	f442 7280 	orr.w	r2, r2, #256	; 0x100
 80018d0:	601a      	str	r2, [r3, #0]

      /* Wait until SB flag is set */
      if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK)
 80018d2:	69fb      	ldr	r3, [r7, #28]
 80018d4:	9300      	str	r3, [sp, #0]
 80018d6:	683b      	ldr	r3, [r7, #0]
 80018d8:	2200      	movs	r2, #0
 80018da:	f04f 1101 	mov.w	r1, #65537	; 0x10001
 80018de:	68f8      	ldr	r0, [r7, #12]
 80018e0:	f000 f952 	bl	8001b88 <I2C_WaitOnFlagUntilTimeout>
 80018e4:	4603      	mov	r3, r0
 80018e6:	2b00      	cmp	r3, #0
 80018e8:	d00d      	beq.n	8001906 <HAL_I2C_IsDeviceReady+0xde>
      {
        if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
 80018ea:	68fb      	ldr	r3, [r7, #12]
 80018ec:	681b      	ldr	r3, [r3, #0]
 80018ee:	681b      	ldr	r3, [r3, #0]
 80018f0:	f403 7380 	and.w	r3, r3, #256	; 0x100
 80018f4:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
 80018f8:	d103      	bne.n	8001902 <HAL_I2C_IsDeviceReady+0xda>
        {
          hi2c->ErrorCode = HAL_I2C_WRONG_START;
 80018fa:	68fb      	ldr	r3, [r7, #12]
 80018fc:	f44f 7200 	mov.w	r2, #512	; 0x200
 8001900:	641a      	str	r2, [r3, #64]	; 0x40
        }
        return HAL_TIMEOUT;
 8001902:	2303      	movs	r3, #3
 8001904:	e0b6      	b.n	8001a74 <HAL_I2C_IsDeviceReady+0x24c>
      }

      /* Send slave address */
      hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
 8001906:	897b      	ldrh	r3, [r7, #10]
 8001908:	b2db      	uxtb	r3, r3
 800190a:	461a      	mov	r2, r3
 800190c:	68fb      	ldr	r3, [r7, #12]
 800190e:	681b      	ldr	r3, [r3, #0]
 8001910:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
 8001914:	611a      	str	r2, [r3, #16]

      /* Wait until ADDR or AF flag are set */
      /* Get tick */
      tickstart = HAL_GetTick();
 8001916:	f7ff faaf 	bl	8000e78 <HAL_GetTick>
 800191a:	61f8      	str	r0, [r7, #28]

      tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
 800191c:	68fb      	ldr	r3, [r7, #12]
 800191e:	681b      	ldr	r3, [r3, #0]
 8001920:	695b      	ldr	r3, [r3, #20]
 8001922:	f003 0302 	and.w	r3, r3, #2
 8001926:	2b02      	cmp	r3, #2
 8001928:	bf0c      	ite	eq
 800192a:	2301      	moveq	r3, #1
 800192c:	2300      	movne	r3, #0
 800192e:	b2db      	uxtb	r3, r3
 8001930:	75fb      	strb	r3, [r7, #23]
      tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
 8001932:	68fb      	ldr	r3, [r7, #12]
 8001934:	681b      	ldr	r3, [r3, #0]
 8001936:	695b      	ldr	r3, [r3, #20]
 8001938:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 800193c:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
 8001940:	bf0c      	ite	eq
 8001942:	2301      	moveq	r3, #1
 8001944:	2300      	movne	r3, #0
 8001946:	b2db      	uxtb	r3, r3
 8001948:	75bb      	strb	r3, [r7, #22]
      while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET))
 800194a:	e025      	b.n	8001998 <HAL_I2C_IsDeviceReady+0x170>
      {
        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
 800194c:	f7ff fa94 	bl	8000e78 <HAL_GetTick>
 8001950:	4602      	mov	r2, r0
 8001952:	69fb      	ldr	r3, [r7, #28]
 8001954:	1ad3      	subs	r3, r2, r3
 8001956:	683a      	ldr	r2, [r7, #0]
 8001958:	429a      	cmp	r2, r3
 800195a:	d302      	bcc.n	8001962 <HAL_I2C_IsDeviceReady+0x13a>
 800195c:	683b      	ldr	r3, [r7, #0]
 800195e:	2b00      	cmp	r3, #0
 8001960:	d103      	bne.n	800196a <HAL_I2C_IsDeviceReady+0x142>
        {
          hi2c->State = HAL_I2C_STATE_TIMEOUT;
 8001962:	68fb      	ldr	r3, [r7, #12]
 8001964:	22a0      	movs	r2, #160	; 0xa0
 8001966:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
        }
        tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR);
 800196a:	68fb      	ldr	r3, [r7, #12]
 800196c:	681b      	ldr	r3, [r3, #0]
 800196e:	695b      	ldr	r3, [r3, #20]
 8001970:	f003 0302 	and.w	r3, r3, #2
 8001974:	2b02      	cmp	r3, #2
 8001976:	bf0c      	ite	eq
 8001978:	2301      	moveq	r3, #1
 800197a:	2300      	movne	r3, #0
 800197c:	b2db      	uxtb	r3, r3
 800197e:	75fb      	strb	r3, [r7, #23]
        tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF);
 8001980:	68fb      	ldr	r3, [r7, #12]
 8001982:	681b      	ldr	r3, [r3, #0]
 8001984:	695b      	ldr	r3, [r3, #20]
 8001986:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 800198a:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
 800198e:	bf0c      	ite	eq
 8001990:	2301      	moveq	r3, #1
 8001992:	2300      	movne	r3, #0
 8001994:	b2db      	uxtb	r3, r3
 8001996:	75bb      	strb	r3, [r7, #22]
      while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET))
 8001998:	68fb      	ldr	r3, [r7, #12]
 800199a:	f893 303d 	ldrb.w	r3, [r3, #61]	; 0x3d
 800199e:	b2db      	uxtb	r3, r3
 80019a0:	2ba0      	cmp	r3, #160	; 0xa0
 80019a2:	d005      	beq.n	80019b0 <HAL_I2C_IsDeviceReady+0x188>
 80019a4:	7dfb      	ldrb	r3, [r7, #23]
 80019a6:	2b00      	cmp	r3, #0
 80019a8:	d102      	bne.n	80019b0 <HAL_I2C_IsDeviceReady+0x188>
 80019aa:	7dbb      	ldrb	r3, [r7, #22]
 80019ac:	2b00      	cmp	r3, #0
 80019ae:	d0cd      	beq.n	800194c <HAL_I2C_IsDeviceReady+0x124>
      }

      hi2c->State = HAL_I2C_STATE_READY;
 80019b0:	68fb      	ldr	r3, [r7, #12]
 80019b2:	2220      	movs	r2, #32
 80019b4:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

      /* Check if the ADDR flag has been set */
      if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
 80019b8:	68fb      	ldr	r3, [r7, #12]
 80019ba:	681b      	ldr	r3, [r3, #0]
 80019bc:	695b      	ldr	r3, [r3, #20]
 80019be:	f003 0302 	and.w	r3, r3, #2
 80019c2:	2b02      	cmp	r3, #2
 80019c4:	d129      	bne.n	8001a1a <HAL_I2C_IsDeviceReady+0x1f2>
      {
        /* Generate Stop */
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 80019c6:	68fb      	ldr	r3, [r7, #12]
 80019c8:	681b      	ldr	r3, [r3, #0]
 80019ca:	681a      	ldr	r2, [r3, #0]
 80019cc:	68fb      	ldr	r3, [r7, #12]
 80019ce:	681b      	ldr	r3, [r3, #0]
 80019d0:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 80019d4:	601a      	str	r2, [r3, #0]

        /* Clear ADDR Flag */
        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
 80019d6:	2300      	movs	r3, #0
 80019d8:	613b      	str	r3, [r7, #16]
 80019da:	68fb      	ldr	r3, [r7, #12]
 80019dc:	681b      	ldr	r3, [r3, #0]
 80019de:	695b      	ldr	r3, [r3, #20]
 80019e0:	613b      	str	r3, [r7, #16]
 80019e2:	68fb      	ldr	r3, [r7, #12]
 80019e4:	681b      	ldr	r3, [r3, #0]
 80019e6:	699b      	ldr	r3, [r3, #24]
 80019e8:	613b      	str	r3, [r7, #16]
 80019ea:	693b      	ldr	r3, [r7, #16]

        /* Wait until BUSY flag is reset */
        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
 80019ec:	69fb      	ldr	r3, [r7, #28]
 80019ee:	9300      	str	r3, [sp, #0]
 80019f0:	2319      	movs	r3, #25
 80019f2:	2201      	movs	r2, #1
 80019f4:	4921      	ldr	r1, [pc, #132]	; (8001a7c <HAL_I2C_IsDeviceReady+0x254>)
 80019f6:	68f8      	ldr	r0, [r7, #12]
 80019f8:	f000 f8c6 	bl	8001b88 <I2C_WaitOnFlagUntilTimeout>
 80019fc:	4603      	mov	r3, r0
 80019fe:	2b00      	cmp	r3, #0
 8001a00:	d001      	beq.n	8001a06 <HAL_I2C_IsDeviceReady+0x1de>
        {
          return HAL_ERROR;
 8001a02:	2301      	movs	r3, #1
 8001a04:	e036      	b.n	8001a74 <HAL_I2C_IsDeviceReady+0x24c>
        }

        hi2c->State = HAL_I2C_STATE_READY;
 8001a06:	68fb      	ldr	r3, [r7, #12]
 8001a08:	2220      	movs	r2, #32
 8001a0a:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

        /* Process Unlocked */
        __HAL_UNLOCK(hi2c);
 8001a0e:	68fb      	ldr	r3, [r7, #12]
 8001a10:	2200      	movs	r2, #0
 8001a12:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

        return HAL_OK;
 8001a16:	2300      	movs	r3, #0
 8001a18:	e02c      	b.n	8001a74 <HAL_I2C_IsDeviceReady+0x24c>
      }
      else
      {
        /* Generate Stop */
        SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 8001a1a:	68fb      	ldr	r3, [r7, #12]
 8001a1c:	681b      	ldr	r3, [r3, #0]
 8001a1e:	681a      	ldr	r2, [r3, #0]
 8001a20:	68fb      	ldr	r3, [r7, #12]
 8001a22:	681b      	ldr	r3, [r3, #0]
 8001a24:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 8001a28:	601a      	str	r2, [r3, #0]

        /* Clear AF Flag */
        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
 8001a2a:	68fb      	ldr	r3, [r7, #12]
 8001a2c:	681b      	ldr	r3, [r3, #0]
 8001a2e:	f46f 6280 	mvn.w	r2, #1024	; 0x400
 8001a32:	615a      	str	r2, [r3, #20]

        /* Wait until BUSY flag is reset */
        if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK)
 8001a34:	69fb      	ldr	r3, [r7, #28]
 8001a36:	9300      	str	r3, [sp, #0]
 8001a38:	2319      	movs	r3, #25
 8001a3a:	2201      	movs	r2, #1
 8001a3c:	490f      	ldr	r1, [pc, #60]	; (8001a7c <HAL_I2C_IsDeviceReady+0x254>)
 8001a3e:	68f8      	ldr	r0, [r7, #12]
 8001a40:	f000 f8a2 	bl	8001b88 <I2C_WaitOnFlagUntilTimeout>
 8001a44:	4603      	mov	r3, r0
 8001a46:	2b00      	cmp	r3, #0
 8001a48:	d001      	beq.n	8001a4e <HAL_I2C_IsDeviceReady+0x226>
        {
          return HAL_ERROR;
 8001a4a:	2301      	movs	r3, #1
 8001a4c:	e012      	b.n	8001a74 <HAL_I2C_IsDeviceReady+0x24c>
        }
      }

      /* Increment Trials */
      I2C_Trials++;
 8001a4e:	69bb      	ldr	r3, [r7, #24]
 8001a50:	3301      	adds	r3, #1
 8001a52:	61bb      	str	r3, [r7, #24]
    }
    while (I2C_Trials < Trials);
 8001a54:	69ba      	ldr	r2, [r7, #24]
 8001a56:	687b      	ldr	r3, [r7, #4]
 8001a58:	429a      	cmp	r2, r3
 8001a5a:	f4ff af32 	bcc.w	80018c2 <HAL_I2C_IsDeviceReady+0x9a>

    hi2c->State = HAL_I2C_STATE_READY;
 8001a5e:	68fb      	ldr	r3, [r7, #12]
 8001a60:	2220      	movs	r2, #32
 8001a62:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);
 8001a66:	68fb      	ldr	r3, [r7, #12]
 8001a68:	2200      	movs	r2, #0
 8001a6a:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    return HAL_ERROR;
 8001a6e:	2301      	movs	r3, #1
 8001a70:	e000      	b.n	8001a74 <HAL_I2C_IsDeviceReady+0x24c>
  }
  else
  {
    return HAL_BUSY;
 8001a72:	2302      	movs	r3, #2
  }
}
 8001a74:	4618      	mov	r0, r3
 8001a76:	3720      	adds	r7, #32
 8001a78:	46bd      	mov	sp, r7
 8001a7a:	bd80      	pop	{r7, pc}
 8001a7c:	00100002 	.word	0x00100002
 8001a80:	ffff0000 	.word	0xffff0000

08001a84 <I2C_MasterRequestWrite>:
  * @param  Timeout Timeout duration
  * @param  Tickstart Tick start value
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart)
{
 8001a84:	b580      	push	{r7, lr}
 8001a86:	b088      	sub	sp, #32
 8001a88:	af02      	add	r7, sp, #8
 8001a8a:	60f8      	str	r0, [r7, #12]
 8001a8c:	607a      	str	r2, [r7, #4]
 8001a8e:	603b      	str	r3, [r7, #0]
 8001a90:	460b      	mov	r3, r1
 8001a92:	817b      	strh	r3, [r7, #10]
  /* Declaration of temporary variable to prevent undefined behavior of volatile usage */
  uint32_t CurrentXferOptions = hi2c->XferOptions;
 8001a94:	68fb      	ldr	r3, [r7, #12]
 8001a96:	6adb      	ldr	r3, [r3, #44]	; 0x2c
 8001a98:	617b      	str	r3, [r7, #20]

  /* Generate Start condition if first transfer */
  if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
 8001a9a:	697b      	ldr	r3, [r7, #20]
 8001a9c:	2b08      	cmp	r3, #8
 8001a9e:	d006      	beq.n	8001aae <I2C_MasterRequestWrite+0x2a>
 8001aa0:	697b      	ldr	r3, [r7, #20]
 8001aa2:	2b01      	cmp	r3, #1
 8001aa4:	d003      	beq.n	8001aae <I2C_MasterRequestWrite+0x2a>
 8001aa6:	697b      	ldr	r3, [r7, #20]
 8001aa8:	f513 3f80 	cmn.w	r3, #65536	; 0x10000
 8001aac:	d108      	bne.n	8001ac0 <I2C_MasterRequestWrite+0x3c>
  {
    /* Generate Start */
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
 8001aae:	68fb      	ldr	r3, [r7, #12]
 8001ab0:	681b      	ldr	r3, [r3, #0]
 8001ab2:	681a      	ldr	r2, [r3, #0]
 8001ab4:	68fb      	ldr	r3, [r7, #12]
 8001ab6:	681b      	ldr	r3, [r3, #0]
 8001ab8:	f442 7280 	orr.w	r2, r2, #256	; 0x100
 8001abc:	601a      	str	r2, [r3, #0]
 8001abe:	e00b      	b.n	8001ad8 <I2C_MasterRequestWrite+0x54>
  }
  else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
 8001ac0:	68fb      	ldr	r3, [r7, #12]
 8001ac2:	6b1b      	ldr	r3, [r3, #48]	; 0x30
 8001ac4:	2b12      	cmp	r3, #18
 8001ac6:	d107      	bne.n	8001ad8 <I2C_MasterRequestWrite+0x54>
  {
    /* Generate ReStart */
    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
 8001ac8:	68fb      	ldr	r3, [r7, #12]
 8001aca:	681b      	ldr	r3, [r3, #0]
 8001acc:	681a      	ldr	r2, [r3, #0]
 8001ace:	68fb      	ldr	r3, [r7, #12]
 8001ad0:	681b      	ldr	r3, [r3, #0]
 8001ad2:	f442 7280 	orr.w	r2, r2, #256	; 0x100
 8001ad6:	601a      	str	r2, [r3, #0]
  {
    /* Do nothing */
  }

  /* Wait until SB flag is set */
  if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK)
 8001ad8:	683b      	ldr	r3, [r7, #0]
 8001ada:	9300      	str	r3, [sp, #0]
 8001adc:	687b      	ldr	r3, [r7, #4]
 8001ade:	2200      	movs	r2, #0
 8001ae0:	f04f 1101 	mov.w	r1, #65537	; 0x10001
 8001ae4:	68f8      	ldr	r0, [r7, #12]
 8001ae6:	f000 f84f 	bl	8001b88 <I2C_WaitOnFlagUntilTimeout>
 8001aea:	4603      	mov	r3, r0
 8001aec:	2b00      	cmp	r3, #0
 8001aee:	d00d      	beq.n	8001b0c <I2C_MasterRequestWrite+0x88>
  {
    if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START)
 8001af0:	68fb      	ldr	r3, [r7, #12]
 8001af2:	681b      	ldr	r3, [r3, #0]
 8001af4:	681b      	ldr	r3, [r3, #0]
 8001af6:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8001afa:	f5b3 7f80 	cmp.w	r3, #256	; 0x100
 8001afe:	d103      	bne.n	8001b08 <I2C_MasterRequestWrite+0x84>
    {
      hi2c->ErrorCode = HAL_I2C_WRONG_START;
 8001b00:	68fb      	ldr	r3, [r7, #12]
 8001b02:	f44f 7200 	mov.w	r2, #512	; 0x200
 8001b06:	641a      	str	r2, [r3, #64]	; 0x40
    }
    return HAL_TIMEOUT;
 8001b08:	2303      	movs	r3, #3
 8001b0a:	e035      	b.n	8001b78 <I2C_MasterRequestWrite+0xf4>
  }

  if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
 8001b0c:	68fb      	ldr	r3, [r7, #12]
 8001b0e:	691b      	ldr	r3, [r3, #16]
 8001b10:	f5b3 4f80 	cmp.w	r3, #16384	; 0x4000
 8001b14:	d108      	bne.n	8001b28 <I2C_MasterRequestWrite+0xa4>
  {
    /* Send slave address */
    hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
 8001b16:	897b      	ldrh	r3, [r7, #10]
 8001b18:	b2db      	uxtb	r3, r3
 8001b1a:	461a      	mov	r2, r3
 8001b1c:	68fb      	ldr	r3, [r7, #12]
 8001b1e:	681b      	ldr	r3, [r3, #0]
 8001b20:	f002 02fe 	and.w	r2, r2, #254	; 0xfe
 8001b24:	611a      	str	r2, [r3, #16]
 8001b26:	e01b      	b.n	8001b60 <I2C_MasterRequestWrite+0xdc>
  }
  else
  {
    /* Send header of slave address */
    hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
 8001b28:	897b      	ldrh	r3, [r7, #10]
 8001b2a:	11db      	asrs	r3, r3, #7
 8001b2c:	b2db      	uxtb	r3, r3
 8001b2e:	f003 0306 	and.w	r3, r3, #6
 8001b32:	b2db      	uxtb	r3, r3
 8001b34:	f063 030f 	orn	r3, r3, #15
 8001b38:	b2da      	uxtb	r2, r3
 8001b3a:	68fb      	ldr	r3, [r7, #12]
 8001b3c:	681b      	ldr	r3, [r3, #0]
 8001b3e:	611a      	str	r2, [r3, #16]

    /* Wait until ADD10 flag is set */
    if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK)
 8001b40:	683b      	ldr	r3, [r7, #0]
 8001b42:	687a      	ldr	r2, [r7, #4]
 8001b44:	490e      	ldr	r1, [pc, #56]	; (8001b80 <I2C_MasterRequestWrite+0xfc>)
 8001b46:	68f8      	ldr	r0, [r7, #12]
 8001b48:	f000 f898 	bl	8001c7c <I2C_WaitOnMasterAddressFlagUntilTimeout>
 8001b4c:	4603      	mov	r3, r0
 8001b4e:	2b00      	cmp	r3, #0
 8001b50:	d001      	beq.n	8001b56 <I2C_MasterRequestWrite+0xd2>
    {
      return HAL_ERROR;
 8001b52:	2301      	movs	r3, #1
 8001b54:	e010      	b.n	8001b78 <I2C_MasterRequestWrite+0xf4>
    }

    /* Send slave address */
    hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
 8001b56:	897b      	ldrh	r3, [r7, #10]
 8001b58:	b2da      	uxtb	r2, r3
 8001b5a:	68fb      	ldr	r3, [r7, #12]
 8001b5c:	681b      	ldr	r3, [r3, #0]
 8001b5e:	611a      	str	r2, [r3, #16]
  }

  /* Wait until ADDR flag is set */
  if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK)
 8001b60:	683b      	ldr	r3, [r7, #0]
 8001b62:	687a      	ldr	r2, [r7, #4]
 8001b64:	4907      	ldr	r1, [pc, #28]	; (8001b84 <I2C_MasterRequestWrite+0x100>)
 8001b66:	68f8      	ldr	r0, [r7, #12]
 8001b68:	f000 f888 	bl	8001c7c <I2C_WaitOnMasterAddressFlagUntilTimeout>
 8001b6c:	4603      	mov	r3, r0
 8001b6e:	2b00      	cmp	r3, #0
 8001b70:	d001      	beq.n	8001b76 <I2C_MasterRequestWrite+0xf2>
  {
    return HAL_ERROR;
 8001b72:	2301      	movs	r3, #1
 8001b74:	e000      	b.n	8001b78 <I2C_MasterRequestWrite+0xf4>
  }

  return HAL_OK;
 8001b76:	2300      	movs	r3, #0
}
 8001b78:	4618      	mov	r0, r3
 8001b7a:	3718      	adds	r7, #24
 8001b7c:	46bd      	mov	sp, r7
 8001b7e:	bd80      	pop	{r7, pc}
 8001b80:	00010008 	.word	0x00010008
 8001b84:	00010002 	.word	0x00010002

08001b88 <I2C_WaitOnFlagUntilTimeout>:
  * @param  Timeout Timeout duration
  * @param  Tickstart Tick start value
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
{
 8001b88:	b580      	push	{r7, lr}
 8001b8a:	b084      	sub	sp, #16
 8001b8c:	af00      	add	r7, sp, #0
 8001b8e:	60f8      	str	r0, [r7, #12]
 8001b90:	60b9      	str	r1, [r7, #8]
 8001b92:	603b      	str	r3, [r7, #0]
 8001b94:	4613      	mov	r3, r2
 8001b96:	71fb      	strb	r3, [r7, #7]
  /* Wait until flag is set */
  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
 8001b98:	e048      	b.n	8001c2c <I2C_WaitOnFlagUntilTimeout+0xa4>
  {
    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 8001b9a:	683b      	ldr	r3, [r7, #0]
 8001b9c:	f1b3 3fff 	cmp.w	r3, #4294967295	; 0xffffffff
 8001ba0:	d044      	beq.n	8001c2c <I2C_WaitOnFlagUntilTimeout+0xa4>
    {
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 8001ba2:	f7ff f969 	bl	8000e78 <HAL_GetTick>
 8001ba6:	4602      	mov	r2, r0
 8001ba8:	69bb      	ldr	r3, [r7, #24]
 8001baa:	1ad3      	subs	r3, r2, r3
 8001bac:	683a      	ldr	r2, [r7, #0]
 8001bae:	429a      	cmp	r2, r3
 8001bb0:	d302      	bcc.n	8001bb8 <I2C_WaitOnFlagUntilTimeout+0x30>
 8001bb2:	683b      	ldr	r3, [r7, #0]
 8001bb4:	2b00      	cmp	r3, #0
 8001bb6:	d139      	bne.n	8001c2c <I2C_WaitOnFlagUntilTimeout+0xa4>
      {
        if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
 8001bb8:	68bb      	ldr	r3, [r7, #8]
 8001bba:	0c1b      	lsrs	r3, r3, #16
 8001bbc:	b2db      	uxtb	r3, r3
 8001bbe:	2b01      	cmp	r3, #1
 8001bc0:	d10d      	bne.n	8001bde <I2C_WaitOnFlagUntilTimeout+0x56>
 8001bc2:	68fb      	ldr	r3, [r7, #12]
 8001bc4:	681b      	ldr	r3, [r3, #0]
 8001bc6:	695b      	ldr	r3, [r3, #20]
 8001bc8:	43da      	mvns	r2, r3
 8001bca:	68bb      	ldr	r3, [r7, #8]
 8001bcc:	4013      	ands	r3, r2
 8001bce:	b29b      	uxth	r3, r3
 8001bd0:	2b00      	cmp	r3, #0
 8001bd2:	bf0c      	ite	eq
 8001bd4:	2301      	moveq	r3, #1
 8001bd6:	2300      	movne	r3, #0
 8001bd8:	b2db      	uxtb	r3, r3
 8001bda:	461a      	mov	r2, r3
 8001bdc:	e00c      	b.n	8001bf8 <I2C_WaitOnFlagUntilTimeout+0x70>
 8001bde:	68fb      	ldr	r3, [r7, #12]
 8001be0:	681b      	ldr	r3, [r3, #0]
 8001be2:	699b      	ldr	r3, [r3, #24]
 8001be4:	43da      	mvns	r2, r3
 8001be6:	68bb      	ldr	r3, [r7, #8]
 8001be8:	4013      	ands	r3, r2
 8001bea:	b29b      	uxth	r3, r3
 8001bec:	2b00      	cmp	r3, #0
 8001bee:	bf0c      	ite	eq
 8001bf0:	2301      	moveq	r3, #1
 8001bf2:	2300      	movne	r3, #0
 8001bf4:	b2db      	uxtb	r3, r3
 8001bf6:	461a      	mov	r2, r3
 8001bf8:	79fb      	ldrb	r3, [r7, #7]
 8001bfa:	429a      	cmp	r2, r3
 8001bfc:	d116      	bne.n	8001c2c <I2C_WaitOnFlagUntilTimeout+0xa4>
        {
          hi2c->PreviousState     = I2C_STATE_NONE;
 8001bfe:	68fb      	ldr	r3, [r7, #12]
 8001c00:	2200      	movs	r2, #0
 8001c02:	631a      	str	r2, [r3, #48]	; 0x30
          hi2c->State             = HAL_I2C_STATE_READY;
 8001c04:	68fb      	ldr	r3, [r7, #12]
 8001c06:	2220      	movs	r2, #32
 8001c08:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
          hi2c->Mode              = HAL_I2C_MODE_NONE;
 8001c0c:	68fb      	ldr	r3, [r7, #12]
 8001c0e:	2200      	movs	r2, #0
 8001c10:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
          hi2c->ErrorCode         |= HAL_I2C_ERROR_TIMEOUT;
 8001c14:	68fb      	ldr	r3, [r7, #12]
 8001c16:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001c18:	f043 0220 	orr.w	r2, r3, #32
 8001c1c:	68fb      	ldr	r3, [r7, #12]
 8001c1e:	641a      	str	r2, [r3, #64]	; 0x40

          /* Process Unlocked */
          __HAL_UNLOCK(hi2c);
 8001c20:	68fb      	ldr	r3, [r7, #12]
 8001c22:	2200      	movs	r2, #0
 8001c24:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

          return HAL_ERROR;
 8001c28:	2301      	movs	r3, #1
 8001c2a:	e023      	b.n	8001c74 <I2C_WaitOnFlagUntilTimeout+0xec>
  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
 8001c2c:	68bb      	ldr	r3, [r7, #8]
 8001c2e:	0c1b      	lsrs	r3, r3, #16
 8001c30:	b2db      	uxtb	r3, r3
 8001c32:	2b01      	cmp	r3, #1
 8001c34:	d10d      	bne.n	8001c52 <I2C_WaitOnFlagUntilTimeout+0xca>
 8001c36:	68fb      	ldr	r3, [r7, #12]
 8001c38:	681b      	ldr	r3, [r3, #0]
 8001c3a:	695b      	ldr	r3, [r3, #20]
 8001c3c:	43da      	mvns	r2, r3
 8001c3e:	68bb      	ldr	r3, [r7, #8]
 8001c40:	4013      	ands	r3, r2
 8001c42:	b29b      	uxth	r3, r3
 8001c44:	2b00      	cmp	r3, #0
 8001c46:	bf0c      	ite	eq
 8001c48:	2301      	moveq	r3, #1
 8001c4a:	2300      	movne	r3, #0
 8001c4c:	b2db      	uxtb	r3, r3
 8001c4e:	461a      	mov	r2, r3
 8001c50:	e00c      	b.n	8001c6c <I2C_WaitOnFlagUntilTimeout+0xe4>
 8001c52:	68fb      	ldr	r3, [r7, #12]
 8001c54:	681b      	ldr	r3, [r3, #0]
 8001c56:	699b      	ldr	r3, [r3, #24]
 8001c58:	43da      	mvns	r2, r3
 8001c5a:	68bb      	ldr	r3, [r7, #8]
 8001c5c:	4013      	ands	r3, r2
 8001c5e:	b29b      	uxth	r3, r3
 8001c60:	2b00      	cmp	r3, #0
 8001c62:	bf0c      	ite	eq
 8001c64:	2301      	moveq	r3, #1
 8001c66:	2300      	movne	r3, #0
 8001c68:	b2db      	uxtb	r3, r3
 8001c6a:	461a      	mov	r2, r3
 8001c6c:	79fb      	ldrb	r3, [r7, #7]
 8001c6e:	429a      	cmp	r2, r3
 8001c70:	d093      	beq.n	8001b9a <I2C_WaitOnFlagUntilTimeout+0x12>
        }
      }
    }
  }
  return HAL_OK;
 8001c72:	2300      	movs	r3, #0
}
 8001c74:	4618      	mov	r0, r3
 8001c76:	3710      	adds	r7, #16
 8001c78:	46bd      	mov	sp, r7
 8001c7a:	bd80      	pop	{r7, pc}

08001c7c <I2C_WaitOnMasterAddressFlagUntilTimeout>:
  * @param  Timeout Timeout duration
  * @param  Tickstart Tick start value
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart)
{
 8001c7c:	b580      	push	{r7, lr}
 8001c7e:	b084      	sub	sp, #16
 8001c80:	af00      	add	r7, sp, #0
 8001c82:	60f8      	str	r0, [r7, #12]
 8001c84:	60b9      	str	r1, [r7, #8]
 8001c86:	607a      	str	r2, [r7, #4]
 8001c88:	603b      	str	r3, [r7, #0]
  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
 8001c8a:	e071      	b.n	8001d70 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
  {
    if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
 8001c8c:	68fb      	ldr	r3, [r7, #12]
 8001c8e:	681b      	ldr	r3, [r3, #0]
 8001c90:	695b      	ldr	r3, [r3, #20]
 8001c92:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 8001c96:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
 8001c9a:	d123      	bne.n	8001ce4 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x68>
    {
      /* Generate Stop */
      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
 8001c9c:	68fb      	ldr	r3, [r7, #12]
 8001c9e:	681b      	ldr	r3, [r3, #0]
 8001ca0:	681a      	ldr	r2, [r3, #0]
 8001ca2:	68fb      	ldr	r3, [r7, #12]
 8001ca4:	681b      	ldr	r3, [r3, #0]
 8001ca6:	f442 7200 	orr.w	r2, r2, #512	; 0x200
 8001caa:	601a      	str	r2, [r3, #0]

      /* Clear AF Flag */
      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
 8001cac:	68fb      	ldr	r3, [r7, #12]
 8001cae:	681b      	ldr	r3, [r3, #0]
 8001cb0:	f46f 6280 	mvn.w	r2, #1024	; 0x400
 8001cb4:	615a      	str	r2, [r3, #20]

      hi2c->PreviousState       = I2C_STATE_NONE;
 8001cb6:	68fb      	ldr	r3, [r7, #12]
 8001cb8:	2200      	movs	r2, #0
 8001cba:	631a      	str	r2, [r3, #48]	; 0x30
      hi2c->State               = HAL_I2C_STATE_READY;
 8001cbc:	68fb      	ldr	r3, [r7, #12]
 8001cbe:	2220      	movs	r2, #32
 8001cc0:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
      hi2c->Mode                = HAL_I2C_MODE_NONE;
 8001cc4:	68fb      	ldr	r3, [r7, #12]
 8001cc6:	2200      	movs	r2, #0
 8001cc8:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
      hi2c->ErrorCode           |= HAL_I2C_ERROR_AF;
 8001ccc:	68fb      	ldr	r3, [r7, #12]
 8001cce:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001cd0:	f043 0204 	orr.w	r2, r3, #4
 8001cd4:	68fb      	ldr	r3, [r7, #12]
 8001cd6:	641a      	str	r2, [r3, #64]	; 0x40

      /* Process Unlocked */
      __HAL_UNLOCK(hi2c);
 8001cd8:	68fb      	ldr	r3, [r7, #12]
 8001cda:	2200      	movs	r2, #0
 8001cdc:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

      return HAL_ERROR;
 8001ce0:	2301      	movs	r3, #1
 8001ce2:	e067      	b.n	8001db4 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x138>
    }

    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 8001ce4:	687b      	ldr	r3, [r7, #4]
 8001ce6:	f1b3 3fff 	cmp.w	r3, #4294967295	; 0xffffffff
 8001cea:	d041      	beq.n	8001d70 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
    {
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 8001cec:	f7ff f8c4 	bl	8000e78 <HAL_GetTick>
 8001cf0:	4602      	mov	r2, r0
 8001cf2:	683b      	ldr	r3, [r7, #0]
 8001cf4:	1ad3      	subs	r3, r2, r3
 8001cf6:	687a      	ldr	r2, [r7, #4]
 8001cf8:	429a      	cmp	r2, r3
 8001cfa:	d302      	bcc.n	8001d02 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x86>
 8001cfc:	687b      	ldr	r3, [r7, #4]
 8001cfe:	2b00      	cmp	r3, #0
 8001d00:	d136      	bne.n	8001d70 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
      {
        if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET))
 8001d02:	68bb      	ldr	r3, [r7, #8]
 8001d04:	0c1b      	lsrs	r3, r3, #16
 8001d06:	b2db      	uxtb	r3, r3
 8001d08:	2b01      	cmp	r3, #1
 8001d0a:	d10c      	bne.n	8001d26 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xaa>
 8001d0c:	68fb      	ldr	r3, [r7, #12]
 8001d0e:	681b      	ldr	r3, [r3, #0]
 8001d10:	695b      	ldr	r3, [r3, #20]
 8001d12:	43da      	mvns	r2, r3
 8001d14:	68bb      	ldr	r3, [r7, #8]
 8001d16:	4013      	ands	r3, r2
 8001d18:	b29b      	uxth	r3, r3
 8001d1a:	2b00      	cmp	r3, #0
 8001d1c:	bf14      	ite	ne
 8001d1e:	2301      	movne	r3, #1
 8001d20:	2300      	moveq	r3, #0
 8001d22:	b2db      	uxtb	r3, r3
 8001d24:	e00b      	b.n	8001d3e <I2C_WaitOnMasterAddressFlagUntilTimeout+0xc2>
 8001d26:	68fb      	ldr	r3, [r7, #12]
 8001d28:	681b      	ldr	r3, [r3, #0]
 8001d2a:	699b      	ldr	r3, [r3, #24]
 8001d2c:	43da      	mvns	r2, r3
 8001d2e:	68bb      	ldr	r3, [r7, #8]
 8001d30:	4013      	ands	r3, r2
 8001d32:	b29b      	uxth	r3, r3
 8001d34:	2b00      	cmp	r3, #0
 8001d36:	bf14      	ite	ne
 8001d38:	2301      	movne	r3, #1
 8001d3a:	2300      	moveq	r3, #0
 8001d3c:	b2db      	uxtb	r3, r3
 8001d3e:	2b00      	cmp	r3, #0
 8001d40:	d016      	beq.n	8001d70 <I2C_WaitOnMasterAddressFlagUntilTimeout+0xf4>
        {
          hi2c->PreviousState       = I2C_STATE_NONE;
 8001d42:	68fb      	ldr	r3, [r7, #12]
 8001d44:	2200      	movs	r2, #0
 8001d46:	631a      	str	r2, [r3, #48]	; 0x30
          hi2c->State               = HAL_I2C_STATE_READY;
 8001d48:	68fb      	ldr	r3, [r7, #12]
 8001d4a:	2220      	movs	r2, #32
 8001d4c:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
          hi2c->Mode                = HAL_I2C_MODE_NONE;
 8001d50:	68fb      	ldr	r3, [r7, #12]
 8001d52:	2200      	movs	r2, #0
 8001d54:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
 8001d58:	68fb      	ldr	r3, [r7, #12]
 8001d5a:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001d5c:	f043 0220 	orr.w	r2, r3, #32
 8001d60:	68fb      	ldr	r3, [r7, #12]
 8001d62:	641a      	str	r2, [r3, #64]	; 0x40

          /* Process Unlocked */
          __HAL_UNLOCK(hi2c);
 8001d64:	68fb      	ldr	r3, [r7, #12]
 8001d66:	2200      	movs	r2, #0
 8001d68:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

          return HAL_ERROR;
 8001d6c:	2301      	movs	r3, #1
 8001d6e:	e021      	b.n	8001db4 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x138>
  while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
 8001d70:	68bb      	ldr	r3, [r7, #8]
 8001d72:	0c1b      	lsrs	r3, r3, #16
 8001d74:	b2db      	uxtb	r3, r3
 8001d76:	2b01      	cmp	r3, #1
 8001d78:	d10c      	bne.n	8001d94 <I2C_WaitOnMasterAddressFlagUntilTimeout+0x118>
 8001d7a:	68fb      	ldr	r3, [r7, #12]
 8001d7c:	681b      	ldr	r3, [r3, #0]
 8001d7e:	695b      	ldr	r3, [r3, #20]
 8001d80:	43da      	mvns	r2, r3
 8001d82:	68bb      	ldr	r3, [r7, #8]
 8001d84:	4013      	ands	r3, r2
 8001d86:	b29b      	uxth	r3, r3
 8001d88:	2b00      	cmp	r3, #0
 8001d8a:	bf14      	ite	ne
 8001d8c:	2301      	movne	r3, #1
 8001d8e:	2300      	moveq	r3, #0
 8001d90:	b2db      	uxtb	r3, r3
 8001d92:	e00b      	b.n	8001dac <I2C_WaitOnMasterAddressFlagUntilTimeout+0x130>
 8001d94:	68fb      	ldr	r3, [r7, #12]
 8001d96:	681b      	ldr	r3, [r3, #0]
 8001d98:	699b      	ldr	r3, [r3, #24]
 8001d9a:	43da      	mvns	r2, r3
 8001d9c:	68bb      	ldr	r3, [r7, #8]
 8001d9e:	4013      	ands	r3, r2
 8001da0:	b29b      	uxth	r3, r3
 8001da2:	2b00      	cmp	r3, #0
 8001da4:	bf14      	ite	ne
 8001da6:	2301      	movne	r3, #1
 8001da8:	2300      	moveq	r3, #0
 8001daa:	b2db      	uxtb	r3, r3
 8001dac:	2b00      	cmp	r3, #0
 8001dae:	f47f af6d 	bne.w	8001c8c <I2C_WaitOnMasterAddressFlagUntilTimeout+0x10>
        }
      }
    }
  }
  return HAL_OK;
 8001db2:	2300      	movs	r3, #0
}
 8001db4:	4618      	mov	r0, r3
 8001db6:	3710      	adds	r7, #16
 8001db8:	46bd      	mov	sp, r7
 8001dba:	bd80      	pop	{r7, pc}

08001dbc <I2C_WaitOnTXEFlagUntilTimeout>:
  * @param  Timeout Timeout duration
  * @param  Tickstart Tick start value
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
 8001dbc:	b580      	push	{r7, lr}
 8001dbe:	b084      	sub	sp, #16
 8001dc0:	af00      	add	r7, sp, #0
 8001dc2:	60f8      	str	r0, [r7, #12]
 8001dc4:	60b9      	str	r1, [r7, #8]
 8001dc6:	607a      	str	r2, [r7, #4]
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
 8001dc8:	e034      	b.n	8001e34 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
  {
    /* Check if a NACK is detected */
    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
 8001dca:	68f8      	ldr	r0, [r7, #12]
 8001dcc:	f000 f886 	bl	8001edc <I2C_IsAcknowledgeFailed>
 8001dd0:	4603      	mov	r3, r0
 8001dd2:	2b00      	cmp	r3, #0
 8001dd4:	d001      	beq.n	8001dda <I2C_WaitOnTXEFlagUntilTimeout+0x1e>
    {
      return HAL_ERROR;
 8001dd6:	2301      	movs	r3, #1
 8001dd8:	e034      	b.n	8001e44 <I2C_WaitOnTXEFlagUntilTimeout+0x88>
    }

    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 8001dda:	68bb      	ldr	r3, [r7, #8]
 8001ddc:	f1b3 3fff 	cmp.w	r3, #4294967295	; 0xffffffff
 8001de0:	d028      	beq.n	8001e34 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
    {
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 8001de2:	f7ff f849 	bl	8000e78 <HAL_GetTick>
 8001de6:	4602      	mov	r2, r0
 8001de8:	687b      	ldr	r3, [r7, #4]
 8001dea:	1ad3      	subs	r3, r2, r3
 8001dec:	68ba      	ldr	r2, [r7, #8]
 8001dee:	429a      	cmp	r2, r3
 8001df0:	d302      	bcc.n	8001df8 <I2C_WaitOnTXEFlagUntilTimeout+0x3c>
 8001df2:	68bb      	ldr	r3, [r7, #8]
 8001df4:	2b00      	cmp	r3, #0
 8001df6:	d11d      	bne.n	8001e34 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
      {
        if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET))
 8001df8:	68fb      	ldr	r3, [r7, #12]
 8001dfa:	681b      	ldr	r3, [r3, #0]
 8001dfc:	695b      	ldr	r3, [r3, #20]
 8001dfe:	f003 0380 	and.w	r3, r3, #128	; 0x80
 8001e02:	2b80      	cmp	r3, #128	; 0x80
 8001e04:	d016      	beq.n	8001e34 <I2C_WaitOnTXEFlagUntilTimeout+0x78>
        {
          hi2c->PreviousState       = I2C_STATE_NONE;
 8001e06:	68fb      	ldr	r3, [r7, #12]
 8001e08:	2200      	movs	r2, #0
 8001e0a:	631a      	str	r2, [r3, #48]	; 0x30
          hi2c->State               = HAL_I2C_STATE_READY;
 8001e0c:	68fb      	ldr	r3, [r7, #12]
 8001e0e:	2220      	movs	r2, #32
 8001e10:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
          hi2c->Mode                = HAL_I2C_MODE_NONE;
 8001e14:	68fb      	ldr	r3, [r7, #12]
 8001e16:	2200      	movs	r2, #0
 8001e18:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
 8001e1c:	68fb      	ldr	r3, [r7, #12]
 8001e1e:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001e20:	f043 0220 	orr.w	r2, r3, #32
 8001e24:	68fb      	ldr	r3, [r7, #12]
 8001e26:	641a      	str	r2, [r3, #64]	; 0x40

          /* Process Unlocked */
          __HAL_UNLOCK(hi2c);
 8001e28:	68fb      	ldr	r3, [r7, #12]
 8001e2a:	2200      	movs	r2, #0
 8001e2c:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

          return HAL_ERROR;
 8001e30:	2301      	movs	r3, #1
 8001e32:	e007      	b.n	8001e44 <I2C_WaitOnTXEFlagUntilTimeout+0x88>
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
 8001e34:	68fb      	ldr	r3, [r7, #12]
 8001e36:	681b      	ldr	r3, [r3, #0]
 8001e38:	695b      	ldr	r3, [r3, #20]
 8001e3a:	f003 0380 	and.w	r3, r3, #128	; 0x80
 8001e3e:	2b80      	cmp	r3, #128	; 0x80
 8001e40:	d1c3      	bne.n	8001dca <I2C_WaitOnTXEFlagUntilTimeout+0xe>
        }
      }
    }
  }
  return HAL_OK;
 8001e42:	2300      	movs	r3, #0
}
 8001e44:	4618      	mov	r0, r3
 8001e46:	3710      	adds	r7, #16
 8001e48:	46bd      	mov	sp, r7
 8001e4a:	bd80      	pop	{r7, pc}

08001e4c <I2C_WaitOnBTFFlagUntilTimeout>:
  * @param  Timeout Timeout duration
  * @param  Tickstart Tick start value
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
 8001e4c:	b580      	push	{r7, lr}
 8001e4e:	b084      	sub	sp, #16
 8001e50:	af00      	add	r7, sp, #0
 8001e52:	60f8      	str	r0, [r7, #12]
 8001e54:	60b9      	str	r1, [r7, #8]
 8001e56:	607a      	str	r2, [r7, #4]
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
 8001e58:	e034      	b.n	8001ec4 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
  {
    /* Check if a NACK is detected */
    if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK)
 8001e5a:	68f8      	ldr	r0, [r7, #12]
 8001e5c:	f000 f83e 	bl	8001edc <I2C_IsAcknowledgeFailed>
 8001e60:	4603      	mov	r3, r0
 8001e62:	2b00      	cmp	r3, #0
 8001e64:	d001      	beq.n	8001e6a <I2C_WaitOnBTFFlagUntilTimeout+0x1e>
    {
      return HAL_ERROR;
 8001e66:	2301      	movs	r3, #1
 8001e68:	e034      	b.n	8001ed4 <I2C_WaitOnBTFFlagUntilTimeout+0x88>
    }

    /* Check for the Timeout */
    if (Timeout != HAL_MAX_DELAY)
 8001e6a:	68bb      	ldr	r3, [r7, #8]
 8001e6c:	f1b3 3fff 	cmp.w	r3, #4294967295	; 0xffffffff
 8001e70:	d028      	beq.n	8001ec4 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
    {
      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
 8001e72:	f7ff f801 	bl	8000e78 <HAL_GetTick>
 8001e76:	4602      	mov	r2, r0
 8001e78:	687b      	ldr	r3, [r7, #4]
 8001e7a:	1ad3      	subs	r3, r2, r3
 8001e7c:	68ba      	ldr	r2, [r7, #8]
 8001e7e:	429a      	cmp	r2, r3
 8001e80:	d302      	bcc.n	8001e88 <I2C_WaitOnBTFFlagUntilTimeout+0x3c>
 8001e82:	68bb      	ldr	r3, [r7, #8]
 8001e84:	2b00      	cmp	r3, #0
 8001e86:	d11d      	bne.n	8001ec4 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
      {
        if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET))
 8001e88:	68fb      	ldr	r3, [r7, #12]
 8001e8a:	681b      	ldr	r3, [r3, #0]
 8001e8c:	695b      	ldr	r3, [r3, #20]
 8001e8e:	f003 0304 	and.w	r3, r3, #4
 8001e92:	2b04      	cmp	r3, #4
 8001e94:	d016      	beq.n	8001ec4 <I2C_WaitOnBTFFlagUntilTimeout+0x78>
        {
          hi2c->PreviousState       = I2C_STATE_NONE;
 8001e96:	68fb      	ldr	r3, [r7, #12]
 8001e98:	2200      	movs	r2, #0
 8001e9a:	631a      	str	r2, [r3, #48]	; 0x30
          hi2c->State               = HAL_I2C_STATE_READY;
 8001e9c:	68fb      	ldr	r3, [r7, #12]
 8001e9e:	2220      	movs	r2, #32
 8001ea0:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
          hi2c->Mode                = HAL_I2C_MODE_NONE;
 8001ea4:	68fb      	ldr	r3, [r7, #12]
 8001ea6:	2200      	movs	r2, #0
 8001ea8:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
          hi2c->ErrorCode           |= HAL_I2C_ERROR_TIMEOUT;
 8001eac:	68fb      	ldr	r3, [r7, #12]
 8001eae:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001eb0:	f043 0220 	orr.w	r2, r3, #32
 8001eb4:	68fb      	ldr	r3, [r7, #12]
 8001eb6:	641a      	str	r2, [r3, #64]	; 0x40

          /* Process Unlocked */
          __HAL_UNLOCK(hi2c);
 8001eb8:	68fb      	ldr	r3, [r7, #12]
 8001eba:	2200      	movs	r2, #0
 8001ebc:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

          return HAL_ERROR;
 8001ec0:	2301      	movs	r3, #1
 8001ec2:	e007      	b.n	8001ed4 <I2C_WaitOnBTFFlagUntilTimeout+0x88>
  while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)
 8001ec4:	68fb      	ldr	r3, [r7, #12]
 8001ec6:	681b      	ldr	r3, [r3, #0]
 8001ec8:	695b      	ldr	r3, [r3, #20]
 8001eca:	f003 0304 	and.w	r3, r3, #4
 8001ece:	2b04      	cmp	r3, #4
 8001ed0:	d1c3      	bne.n	8001e5a <I2C_WaitOnBTFFlagUntilTimeout+0xe>
        }
      }
    }
  }
  return HAL_OK;
 8001ed2:	2300      	movs	r3, #0
}
 8001ed4:	4618      	mov	r0, r3
 8001ed6:	3710      	adds	r7, #16
 8001ed8:	46bd      	mov	sp, r7
 8001eda:	bd80      	pop	{r7, pc}

08001edc <I2C_IsAcknowledgeFailed>:
  * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
  *                the configuration information for the specified I2C.
  * @retval HAL status
  */
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c)
{
 8001edc:	b480      	push	{r7}
 8001ede:	b083      	sub	sp, #12
 8001ee0:	af00      	add	r7, sp, #0
 8001ee2:	6078      	str	r0, [r7, #4]
  if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
 8001ee4:	687b      	ldr	r3, [r7, #4]
 8001ee6:	681b      	ldr	r3, [r3, #0]
 8001ee8:	695b      	ldr	r3, [r3, #20]
 8001eea:	f403 6380 	and.w	r3, r3, #1024	; 0x400
 8001eee:	f5b3 6f80 	cmp.w	r3, #1024	; 0x400
 8001ef2:	d11b      	bne.n	8001f2c <I2C_IsAcknowledgeFailed+0x50>
  {
    /* Clear NACKF Flag */
    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
 8001ef4:	687b      	ldr	r3, [r7, #4]
 8001ef6:	681b      	ldr	r3, [r3, #0]
 8001ef8:	f46f 6280 	mvn.w	r2, #1024	; 0x400
 8001efc:	615a      	str	r2, [r3, #20]

    hi2c->PreviousState       = I2C_STATE_NONE;
 8001efe:	687b      	ldr	r3, [r7, #4]
 8001f00:	2200      	movs	r2, #0
 8001f02:	631a      	str	r2, [r3, #48]	; 0x30
    hi2c->State               = HAL_I2C_STATE_READY;
 8001f04:	687b      	ldr	r3, [r7, #4]
 8001f06:	2220      	movs	r2, #32
 8001f08:	f883 203d 	strb.w	r2, [r3, #61]	; 0x3d
    hi2c->Mode                = HAL_I2C_MODE_NONE;
 8001f0c:	687b      	ldr	r3, [r7, #4]
 8001f0e:	2200      	movs	r2, #0
 8001f10:	f883 203e 	strb.w	r2, [r3, #62]	; 0x3e
    hi2c->ErrorCode           |= HAL_I2C_ERROR_AF;
 8001f14:	687b      	ldr	r3, [r7, #4]
 8001f16:	6c1b      	ldr	r3, [r3, #64]	; 0x40
 8001f18:	f043 0204 	orr.w	r2, r3, #4
 8001f1c:	687b      	ldr	r3, [r7, #4]
 8001f1e:	641a      	str	r2, [r3, #64]	; 0x40

    /* Process Unlocked */
    __HAL_UNLOCK(hi2c);
 8001f20:	687b      	ldr	r3, [r7, #4]
 8001f22:	2200      	movs	r2, #0
 8001f24:	f883 203c 	strb.w	r2, [r3, #60]	; 0x3c

    return HAL_ERROR;
 8001f28:	2301      	movs	r3, #1
 8001f2a:	e000      	b.n	8001f2e <I2C_IsAcknowledgeFailed+0x52>
  }
  return HAL_OK;
 8001f2c:	2300      	movs	r3, #0
}
 8001f2e:	4618      	mov	r0, r3
 8001f30:	370c      	adds	r7, #12
 8001f32:	46bd      	mov	sp, r7
 8001f34:	bc80      	pop	{r7}
 8001f36:	4770      	bx	lr

08001f38 <HAL_RCC_OscConfig>:
  *         supported by this macro. User should request a transition to HSE Off
  *         first and then HSE On or HSE Bypass.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
{
 8001f38:	b580      	push	{r7, lr}
 8001f3a:	b086      	sub	sp, #24
 8001f3c:	af00      	add	r7, sp, #0
 8001f3e:	6078      	str	r0, [r7, #4]
  uint32_t tickstart;
  uint32_t pll_config;

  /* Check Null pointer */
  if (RCC_OscInitStruct == NULL)
 8001f40:	687b      	ldr	r3, [r7, #4]
 8001f42:	2b00      	cmp	r3, #0
 8001f44:	d101      	bne.n	8001f4a <HAL_RCC_OscConfig+0x12>
  {
    return HAL_ERROR;
 8001f46:	2301      	movs	r3, #1
 8001f48:	e272      	b.n	8002430 <HAL_RCC_OscConfig+0x4f8>

  /* Check the parameters */
  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));

  /*------------------------------- HSE Configuration ------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
 8001f4a:	687b      	ldr	r3, [r7, #4]
 8001f4c:	681b      	ldr	r3, [r3, #0]
 8001f4e:	f003 0301 	and.w	r3, r3, #1
 8001f52:	2b00      	cmp	r3, #0
 8001f54:	f000 8087 	beq.w	8002066 <HAL_RCC_OscConfig+0x12e>
  {
    /* Check the parameters */
    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));

    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
 8001f58:	4b92      	ldr	r3, [pc, #584]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8001f5a:	685b      	ldr	r3, [r3, #4]
 8001f5c:	f003 030c 	and.w	r3, r3, #12
 8001f60:	2b04      	cmp	r3, #4
 8001f62:	d00c      	beq.n	8001f7e <HAL_RCC_OscConfig+0x46>
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
 8001f64:	4b8f      	ldr	r3, [pc, #572]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8001f66:	685b      	ldr	r3, [r3, #4]
 8001f68:	f003 030c 	and.w	r3, r3, #12
 8001f6c:	2b08      	cmp	r3, #8
 8001f6e:	d112      	bne.n	8001f96 <HAL_RCC_OscConfig+0x5e>
 8001f70:	4b8c      	ldr	r3, [pc, #560]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8001f72:	685b      	ldr	r3, [r3, #4]
 8001f74:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 8001f78:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8001f7c:	d10b      	bne.n	8001f96 <HAL_RCC_OscConfig+0x5e>
    {
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8001f7e:	4b89      	ldr	r3, [pc, #548]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8001f80:	681b      	ldr	r3, [r3, #0]
 8001f82:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8001f86:	2b00      	cmp	r3, #0
 8001f88:	d06c      	beq.n	8002064 <HAL_RCC_OscConfig+0x12c>
 8001f8a:	687b      	ldr	r3, [r7, #4]
 8001f8c:	685b      	ldr	r3, [r3, #4]
 8001f8e:	2b00      	cmp	r3, #0
 8001f90:	d168      	bne.n	8002064 <HAL_RCC_OscConfig+0x12c>
      {
        return HAL_ERROR;
 8001f92:	2301      	movs	r3, #1
 8001f94:	e24c      	b.n	8002430 <HAL_RCC_OscConfig+0x4f8>
      }
    }
    else
    {
      /* Set the new HSE configuration ---------------------------------------*/
      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
 8001f96:	687b      	ldr	r3, [r7, #4]
 8001f98:	685b      	ldr	r3, [r3, #4]
 8001f9a:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8001f9e:	d106      	bne.n	8001fae <HAL_RCC_OscConfig+0x76>
 8001fa0:	4b80      	ldr	r3, [pc, #512]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8001fa2:	681b      	ldr	r3, [r3, #0]
 8001fa4:	4a7f      	ldr	r2, [pc, #508]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8001fa6:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8001faa:	6013      	str	r3, [r2, #0]
 8001fac:	e02e      	b.n	800200c <HAL_RCC_OscConfig+0xd4>
 8001fae:	687b      	ldr	r3, [r7, #4]
 8001fb0:	685b      	ldr	r3, [r3, #4]
 8001fb2:	2b00      	cmp	r3, #0
 8001fb4:	d10c      	bne.n	8001fd0 <HAL_RCC_OscConfig+0x98>
 8001fb6:	4b7b      	ldr	r3, [pc, #492]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8001fb8:	681b      	ldr	r3, [r3, #0]
 8001fba:	4a7a      	ldr	r2, [pc, #488]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8001fbc:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8001fc0:	6013      	str	r3, [r2, #0]
 8001fc2:	4b78      	ldr	r3, [pc, #480]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8001fc4:	681b      	ldr	r3, [r3, #0]
 8001fc6:	4a77      	ldr	r2, [pc, #476]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8001fc8:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 8001fcc:	6013      	str	r3, [r2, #0]
 8001fce:	e01d      	b.n	800200c <HAL_RCC_OscConfig+0xd4>
 8001fd0:	687b      	ldr	r3, [r7, #4]
 8001fd2:	685b      	ldr	r3, [r3, #4]
 8001fd4:	f5b3 2fa0 	cmp.w	r3, #327680	; 0x50000
 8001fd8:	d10c      	bne.n	8001ff4 <HAL_RCC_OscConfig+0xbc>
 8001fda:	4b72      	ldr	r3, [pc, #456]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8001fdc:	681b      	ldr	r3, [r3, #0]
 8001fde:	4a71      	ldr	r2, [pc, #452]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8001fe0:	f443 2380 	orr.w	r3, r3, #262144	; 0x40000
 8001fe4:	6013      	str	r3, [r2, #0]
 8001fe6:	4b6f      	ldr	r3, [pc, #444]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8001fe8:	681b      	ldr	r3, [r3, #0]
 8001fea:	4a6e      	ldr	r2, [pc, #440]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8001fec:	f443 3380 	orr.w	r3, r3, #65536	; 0x10000
 8001ff0:	6013      	str	r3, [r2, #0]
 8001ff2:	e00b      	b.n	800200c <HAL_RCC_OscConfig+0xd4>
 8001ff4:	4b6b      	ldr	r3, [pc, #428]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8001ff6:	681b      	ldr	r3, [r3, #0]
 8001ff8:	4a6a      	ldr	r2, [pc, #424]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8001ffa:	f423 3380 	bic.w	r3, r3, #65536	; 0x10000
 8001ffe:	6013      	str	r3, [r2, #0]
 8002000:	4b68      	ldr	r3, [pc, #416]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8002002:	681b      	ldr	r3, [r3, #0]
 8002004:	4a67      	ldr	r2, [pc, #412]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8002006:	f423 2380 	bic.w	r3, r3, #262144	; 0x40000
 800200a:	6013      	str	r3, [r2, #0]


      /* Check the HSE State */
      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
 800200c:	687b      	ldr	r3, [r7, #4]
 800200e:	685b      	ldr	r3, [r3, #4]
 8002010:	2b00      	cmp	r3, #0
 8002012:	d013      	beq.n	800203c <HAL_RCC_OscConfig+0x104>
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8002014:	f7fe ff30 	bl	8000e78 <HAL_GetTick>
 8002018:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 800201a:	e008      	b.n	800202e <HAL_RCC_OscConfig+0xf6>
        {
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 800201c:	f7fe ff2c 	bl	8000e78 <HAL_GetTick>
 8002020:	4602      	mov	r2, r0
 8002022:	693b      	ldr	r3, [r7, #16]
 8002024:	1ad3      	subs	r3, r2, r3
 8002026:	2b64      	cmp	r3, #100	; 0x64
 8002028:	d901      	bls.n	800202e <HAL_RCC_OscConfig+0xf6>
          {
            return HAL_TIMEOUT;
 800202a:	2303      	movs	r3, #3
 800202c:	e200      	b.n	8002430 <HAL_RCC_OscConfig+0x4f8>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 800202e:	4b5d      	ldr	r3, [pc, #372]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8002030:	681b      	ldr	r3, [r3, #0]
 8002032:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 8002036:	2b00      	cmp	r3, #0
 8002038:	d0f0      	beq.n	800201c <HAL_RCC_OscConfig+0xe4>
 800203a:	e014      	b.n	8002066 <HAL_RCC_OscConfig+0x12e>
        }
      }
      else
      {
        /* Get Start Tick */
        tickstart = HAL_GetTick();
 800203c:	f7fe ff1c 	bl	8000e78 <HAL_GetTick>
 8002040:	6138      	str	r0, [r7, #16]

        /* Wait till HSE is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 8002042:	e008      	b.n	8002056 <HAL_RCC_OscConfig+0x11e>
        {
          if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
 8002044:	f7fe ff18 	bl	8000e78 <HAL_GetTick>
 8002048:	4602      	mov	r2, r0
 800204a:	693b      	ldr	r3, [r7, #16]
 800204c:	1ad3      	subs	r3, r2, r3
 800204e:	2b64      	cmp	r3, #100	; 0x64
 8002050:	d901      	bls.n	8002056 <HAL_RCC_OscConfig+0x11e>
          {
            return HAL_TIMEOUT;
 8002052:	2303      	movs	r3, #3
 8002054:	e1ec      	b.n	8002430 <HAL_RCC_OscConfig+0x4f8>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
 8002056:	4b53      	ldr	r3, [pc, #332]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8002058:	681b      	ldr	r3, [r3, #0]
 800205a:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 800205e:	2b00      	cmp	r3, #0
 8002060:	d1f0      	bne.n	8002044 <HAL_RCC_OscConfig+0x10c>
 8002062:	e000      	b.n	8002066 <HAL_RCC_OscConfig+0x12e>
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
 8002064:	bf00      	nop
        }
      }
    }
  }
  /*----------------------------- HSI Configuration --------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
 8002066:	687b      	ldr	r3, [r7, #4]
 8002068:	681b      	ldr	r3, [r3, #0]
 800206a:	f003 0302 	and.w	r3, r3, #2
 800206e:	2b00      	cmp	r3, #0
 8002070:	d063      	beq.n	800213a <HAL_RCC_OscConfig+0x202>
    /* Check the parameters */
    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));

    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
    if ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
 8002072:	4b4c      	ldr	r3, [pc, #304]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8002074:	685b      	ldr	r3, [r3, #4]
 8002076:	f003 030c 	and.w	r3, r3, #12
 800207a:	2b00      	cmp	r3, #0
 800207c:	d00b      	beq.n	8002096 <HAL_RCC_OscConfig+0x15e>
        || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI_DIV2)))
 800207e:	4b49      	ldr	r3, [pc, #292]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8002080:	685b      	ldr	r3, [r3, #4]
 8002082:	f003 030c 	and.w	r3, r3, #12
 8002086:	2b08      	cmp	r3, #8
 8002088:	d11c      	bne.n	80020c4 <HAL_RCC_OscConfig+0x18c>
 800208a:	4b46      	ldr	r3, [pc, #280]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 800208c:	685b      	ldr	r3, [r3, #4]
 800208e:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 8002092:	2b00      	cmp	r3, #0
 8002094:	d116      	bne.n	80020c4 <HAL_RCC_OscConfig+0x18c>
    {
      /* When HSI is used as system clock it will not disabled */
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 8002096:	4b43      	ldr	r3, [pc, #268]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8002098:	681b      	ldr	r3, [r3, #0]
 800209a:	f003 0302 	and.w	r3, r3, #2
 800209e:	2b00      	cmp	r3, #0
 80020a0:	d005      	beq.n	80020ae <HAL_RCC_OscConfig+0x176>
 80020a2:	687b      	ldr	r3, [r7, #4]
 80020a4:	691b      	ldr	r3, [r3, #16]
 80020a6:	2b01      	cmp	r3, #1
 80020a8:	d001      	beq.n	80020ae <HAL_RCC_OscConfig+0x176>
      {
        return HAL_ERROR;
 80020aa:	2301      	movs	r3, #1
 80020ac:	e1c0      	b.n	8002430 <HAL_RCC_OscConfig+0x4f8>
      }
      /* Otherwise, just the calibration is allowed */
      else
      {
        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 80020ae:	4b3d      	ldr	r3, [pc, #244]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 80020b0:	681b      	ldr	r3, [r3, #0]
 80020b2:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
 80020b6:	687b      	ldr	r3, [r7, #4]
 80020b8:	695b      	ldr	r3, [r3, #20]
 80020ba:	00db      	lsls	r3, r3, #3
 80020bc:	4939      	ldr	r1, [pc, #228]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 80020be:	4313      	orrs	r3, r2
 80020c0:	600b      	str	r3, [r1, #0]
      if ((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
 80020c2:	e03a      	b.n	800213a <HAL_RCC_OscConfig+0x202>
      }
    }
    else
    {
      /* Check the HSI State */
      if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
 80020c4:	687b      	ldr	r3, [r7, #4]
 80020c6:	691b      	ldr	r3, [r3, #16]
 80020c8:	2b00      	cmp	r3, #0
 80020ca:	d020      	beq.n	800210e <HAL_RCC_OscConfig+0x1d6>
      {
        /* Enable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_ENABLE();
 80020cc:	4b36      	ldr	r3, [pc, #216]	; (80021a8 <HAL_RCC_OscConfig+0x270>)
 80020ce:	2201      	movs	r2, #1
 80020d0:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80020d2:	f7fe fed1 	bl	8000e78 <HAL_GetTick>
 80020d6:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 80020d8:	e008      	b.n	80020ec <HAL_RCC_OscConfig+0x1b4>
        {
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 80020da:	f7fe fecd 	bl	8000e78 <HAL_GetTick>
 80020de:	4602      	mov	r2, r0
 80020e0:	693b      	ldr	r3, [r7, #16]
 80020e2:	1ad3      	subs	r3, r2, r3
 80020e4:	2b02      	cmp	r3, #2
 80020e6:	d901      	bls.n	80020ec <HAL_RCC_OscConfig+0x1b4>
          {
            return HAL_TIMEOUT;
 80020e8:	2303      	movs	r3, #3
 80020ea:	e1a1      	b.n	8002430 <HAL_RCC_OscConfig+0x4f8>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 80020ec:	4b2d      	ldr	r3, [pc, #180]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 80020ee:	681b      	ldr	r3, [r3, #0]
 80020f0:	f003 0302 	and.w	r3, r3, #2
 80020f4:	2b00      	cmp	r3, #0
 80020f6:	d0f0      	beq.n	80020da <HAL_RCC_OscConfig+0x1a2>
          }
        }

        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
 80020f8:	4b2a      	ldr	r3, [pc, #168]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 80020fa:	681b      	ldr	r3, [r3, #0]
 80020fc:	f023 02f8 	bic.w	r2, r3, #248	; 0xf8
 8002100:	687b      	ldr	r3, [r7, #4]
 8002102:	695b      	ldr	r3, [r3, #20]
 8002104:	00db      	lsls	r3, r3, #3
 8002106:	4927      	ldr	r1, [pc, #156]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8002108:	4313      	orrs	r3, r2
 800210a:	600b      	str	r3, [r1, #0]
 800210c:	e015      	b.n	800213a <HAL_RCC_OscConfig+0x202>
      }
      else
      {
        /* Disable the Internal High Speed oscillator (HSI). */
        __HAL_RCC_HSI_DISABLE();
 800210e:	4b26      	ldr	r3, [pc, #152]	; (80021a8 <HAL_RCC_OscConfig+0x270>)
 8002110:	2200      	movs	r2, #0
 8002112:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 8002114:	f7fe feb0 	bl	8000e78 <HAL_GetTick>
 8002118:	6138      	str	r0, [r7, #16]

        /* Wait till HSI is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 800211a:	e008      	b.n	800212e <HAL_RCC_OscConfig+0x1f6>
        {
          if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
 800211c:	f7fe feac 	bl	8000e78 <HAL_GetTick>
 8002120:	4602      	mov	r2, r0
 8002122:	693b      	ldr	r3, [r7, #16]
 8002124:	1ad3      	subs	r3, r2, r3
 8002126:	2b02      	cmp	r3, #2
 8002128:	d901      	bls.n	800212e <HAL_RCC_OscConfig+0x1f6>
          {
            return HAL_TIMEOUT;
 800212a:	2303      	movs	r3, #3
 800212c:	e180      	b.n	8002430 <HAL_RCC_OscConfig+0x4f8>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
 800212e:	4b1d      	ldr	r3, [pc, #116]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8002130:	681b      	ldr	r3, [r3, #0]
 8002132:	f003 0302 	and.w	r3, r3, #2
 8002136:	2b00      	cmp	r3, #0
 8002138:	d1f0      	bne.n	800211c <HAL_RCC_OscConfig+0x1e4>
        }
      }
    }
  }
  /*------------------------------ LSI Configuration -------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
 800213a:	687b      	ldr	r3, [r7, #4]
 800213c:	681b      	ldr	r3, [r3, #0]
 800213e:	f003 0308 	and.w	r3, r3, #8
 8002142:	2b00      	cmp	r3, #0
 8002144:	d03a      	beq.n	80021bc <HAL_RCC_OscConfig+0x284>
  {
    /* Check the parameters */
    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));

    /* Check the LSI State */
    if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
 8002146:	687b      	ldr	r3, [r7, #4]
 8002148:	699b      	ldr	r3, [r3, #24]
 800214a:	2b00      	cmp	r3, #0
 800214c:	d019      	beq.n	8002182 <HAL_RCC_OscConfig+0x24a>
    {
      /* Enable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_ENABLE();
 800214e:	4b17      	ldr	r3, [pc, #92]	; (80021ac <HAL_RCC_OscConfig+0x274>)
 8002150:	2201      	movs	r2, #1
 8002152:	601a      	str	r2, [r3, #0]

      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8002154:	f7fe fe90 	bl	8000e78 <HAL_GetTick>
 8002158:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 800215a:	e008      	b.n	800216e <HAL_RCC_OscConfig+0x236>
      {
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 800215c:	f7fe fe8c 	bl	8000e78 <HAL_GetTick>
 8002160:	4602      	mov	r2, r0
 8002162:	693b      	ldr	r3, [r7, #16]
 8002164:	1ad3      	subs	r3, r2, r3
 8002166:	2b02      	cmp	r3, #2
 8002168:	d901      	bls.n	800216e <HAL_RCC_OscConfig+0x236>
        {
          return HAL_TIMEOUT;
 800216a:	2303      	movs	r3, #3
 800216c:	e160      	b.n	8002430 <HAL_RCC_OscConfig+0x4f8>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
 800216e:	4b0d      	ldr	r3, [pc, #52]	; (80021a4 <HAL_RCC_OscConfig+0x26c>)
 8002170:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 8002172:	f003 0302 	and.w	r3, r3, #2
 8002176:	2b00      	cmp	r3, #0
 8002178:	d0f0      	beq.n	800215c <HAL_RCC_OscConfig+0x224>
        }
      }
      /*  To have a fully stabilized clock in the specified range, a software delay of 1ms
          should be added.*/
      RCC_Delay(1);
 800217a:	2001      	movs	r0, #1
 800217c:	f000 faba 	bl	80026f4 <RCC_Delay>
 8002180:	e01c      	b.n	80021bc <HAL_RCC_OscConfig+0x284>
    }
    else
    {
      /* Disable the Internal Low Speed oscillator (LSI). */
      __HAL_RCC_LSI_DISABLE();
 8002182:	4b0a      	ldr	r3, [pc, #40]	; (80021ac <HAL_RCC_OscConfig+0x274>)
 8002184:	2200      	movs	r2, #0
 8002186:	601a      	str	r2, [r3, #0]

      /* Get Start Tick */
      tickstart = HAL_GetTick();
 8002188:	f7fe fe76 	bl	8000e78 <HAL_GetTick>
 800218c:	6138      	str	r0, [r7, #16]

      /* Wait till LSI is disabled */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 800218e:	e00f      	b.n	80021b0 <HAL_RCC_OscConfig+0x278>
      {
        if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
 8002190:	f7fe fe72 	bl	8000e78 <HAL_GetTick>
 8002194:	4602      	mov	r2, r0
 8002196:	693b      	ldr	r3, [r7, #16]
 8002198:	1ad3      	subs	r3, r2, r3
 800219a:	2b02      	cmp	r3, #2
 800219c:	d908      	bls.n	80021b0 <HAL_RCC_OscConfig+0x278>
        {
          return HAL_TIMEOUT;
 800219e:	2303      	movs	r3, #3
 80021a0:	e146      	b.n	8002430 <HAL_RCC_OscConfig+0x4f8>
 80021a2:	bf00      	nop
 80021a4:	40021000 	.word	0x40021000
 80021a8:	42420000 	.word	0x42420000
 80021ac:	42420480 	.word	0x42420480
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
 80021b0:	4b92      	ldr	r3, [pc, #584]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 80021b2:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 80021b4:	f003 0302 	and.w	r3, r3, #2
 80021b8:	2b00      	cmp	r3, #0
 80021ba:	d1e9      	bne.n	8002190 <HAL_RCC_OscConfig+0x258>
        }
      }
    }
  }
  /*------------------------------ LSE Configuration -------------------------*/
  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
 80021bc:	687b      	ldr	r3, [r7, #4]
 80021be:	681b      	ldr	r3, [r3, #0]
 80021c0:	f003 0304 	and.w	r3, r3, #4
 80021c4:	2b00      	cmp	r3, #0
 80021c6:	f000 80a6 	beq.w	8002316 <HAL_RCC_OscConfig+0x3de>
  {
    FlagStatus       pwrclkchanged = RESET;
 80021ca:	2300      	movs	r3, #0
 80021cc:	75fb      	strb	r3, [r7, #23]
    /* Check the parameters */
    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));

    /* Update LSE configuration in Backup Domain control register    */
    /* Requires to enable write access to Backup Domain of necessary */
    if (__HAL_RCC_PWR_IS_CLK_DISABLED())
 80021ce:	4b8b      	ldr	r3, [pc, #556]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 80021d0:	69db      	ldr	r3, [r3, #28]
 80021d2:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 80021d6:	2b00      	cmp	r3, #0
 80021d8:	d10d      	bne.n	80021f6 <HAL_RCC_OscConfig+0x2be>
    {
      __HAL_RCC_PWR_CLK_ENABLE();
 80021da:	4b88      	ldr	r3, [pc, #544]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 80021dc:	69db      	ldr	r3, [r3, #28]
 80021de:	4a87      	ldr	r2, [pc, #540]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 80021e0:	f043 5380 	orr.w	r3, r3, #268435456	; 0x10000000
 80021e4:	61d3      	str	r3, [r2, #28]
 80021e6:	4b85      	ldr	r3, [pc, #532]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 80021e8:	69db      	ldr	r3, [r3, #28]
 80021ea:	f003 5380 	and.w	r3, r3, #268435456	; 0x10000000
 80021ee:	60bb      	str	r3, [r7, #8]
 80021f0:	68bb      	ldr	r3, [r7, #8]
      pwrclkchanged = SET;
 80021f2:	2301      	movs	r3, #1
 80021f4:	75fb      	strb	r3, [r7, #23]
    }

    if (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 80021f6:	4b82      	ldr	r3, [pc, #520]	; (8002400 <HAL_RCC_OscConfig+0x4c8>)
 80021f8:	681b      	ldr	r3, [r3, #0]
 80021fa:	f403 7380 	and.w	r3, r3, #256	; 0x100
 80021fe:	2b00      	cmp	r3, #0
 8002200:	d118      	bne.n	8002234 <HAL_RCC_OscConfig+0x2fc>
    {
      /* Enable write access to Backup domain */
      SET_BIT(PWR->CR, PWR_CR_DBP);
 8002202:	4b7f      	ldr	r3, [pc, #508]	; (8002400 <HAL_RCC_OscConfig+0x4c8>)
 8002204:	681b      	ldr	r3, [r3, #0]
 8002206:	4a7e      	ldr	r2, [pc, #504]	; (8002400 <HAL_RCC_OscConfig+0x4c8>)
 8002208:	f443 7380 	orr.w	r3, r3, #256	; 0x100
 800220c:	6013      	str	r3, [r2, #0]

      /* Wait for Backup domain Write protection disable */
      tickstart = HAL_GetTick();
 800220e:	f7fe fe33 	bl	8000e78 <HAL_GetTick>
 8002212:	6138      	str	r0, [r7, #16]

      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8002214:	e008      	b.n	8002228 <HAL_RCC_OscConfig+0x2f0>
      {
        if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
 8002216:	f7fe fe2f 	bl	8000e78 <HAL_GetTick>
 800221a:	4602      	mov	r2, r0
 800221c:	693b      	ldr	r3, [r7, #16]
 800221e:	1ad3      	subs	r3, r2, r3
 8002220:	2b64      	cmp	r3, #100	; 0x64
 8002222:	d901      	bls.n	8002228 <HAL_RCC_OscConfig+0x2f0>
        {
          return HAL_TIMEOUT;
 8002224:	2303      	movs	r3, #3
 8002226:	e103      	b.n	8002430 <HAL_RCC_OscConfig+0x4f8>
      while (HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
 8002228:	4b75      	ldr	r3, [pc, #468]	; (8002400 <HAL_RCC_OscConfig+0x4c8>)
 800222a:	681b      	ldr	r3, [r3, #0]
 800222c:	f403 7380 	and.w	r3, r3, #256	; 0x100
 8002230:	2b00      	cmp	r3, #0
 8002232:	d0f0      	beq.n	8002216 <HAL_RCC_OscConfig+0x2de>
        }
      }
    }

    /* Set the new LSE configuration -----------------------------------------*/
    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
 8002234:	687b      	ldr	r3, [r7, #4]
 8002236:	68db      	ldr	r3, [r3, #12]
 8002238:	2b01      	cmp	r3, #1
 800223a:	d106      	bne.n	800224a <HAL_RCC_OscConfig+0x312>
 800223c:	4b6f      	ldr	r3, [pc, #444]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 800223e:	6a1b      	ldr	r3, [r3, #32]
 8002240:	4a6e      	ldr	r2, [pc, #440]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 8002242:	f043 0301 	orr.w	r3, r3, #1
 8002246:	6213      	str	r3, [r2, #32]
 8002248:	e02d      	b.n	80022a6 <HAL_RCC_OscConfig+0x36e>
 800224a:	687b      	ldr	r3, [r7, #4]
 800224c:	68db      	ldr	r3, [r3, #12]
 800224e:	2b00      	cmp	r3, #0
 8002250:	d10c      	bne.n	800226c <HAL_RCC_OscConfig+0x334>
 8002252:	4b6a      	ldr	r3, [pc, #424]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 8002254:	6a1b      	ldr	r3, [r3, #32]
 8002256:	4a69      	ldr	r2, [pc, #420]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 8002258:	f023 0301 	bic.w	r3, r3, #1
 800225c:	6213      	str	r3, [r2, #32]
 800225e:	4b67      	ldr	r3, [pc, #412]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 8002260:	6a1b      	ldr	r3, [r3, #32]
 8002262:	4a66      	ldr	r2, [pc, #408]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 8002264:	f023 0304 	bic.w	r3, r3, #4
 8002268:	6213      	str	r3, [r2, #32]
 800226a:	e01c      	b.n	80022a6 <HAL_RCC_OscConfig+0x36e>
 800226c:	687b      	ldr	r3, [r7, #4]
 800226e:	68db      	ldr	r3, [r3, #12]
 8002270:	2b05      	cmp	r3, #5
 8002272:	d10c      	bne.n	800228e <HAL_RCC_OscConfig+0x356>
 8002274:	4b61      	ldr	r3, [pc, #388]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 8002276:	6a1b      	ldr	r3, [r3, #32]
 8002278:	4a60      	ldr	r2, [pc, #384]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 800227a:	f043 0304 	orr.w	r3, r3, #4
 800227e:	6213      	str	r3, [r2, #32]
 8002280:	4b5e      	ldr	r3, [pc, #376]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 8002282:	6a1b      	ldr	r3, [r3, #32]
 8002284:	4a5d      	ldr	r2, [pc, #372]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 8002286:	f043 0301 	orr.w	r3, r3, #1
 800228a:	6213      	str	r3, [r2, #32]
 800228c:	e00b      	b.n	80022a6 <HAL_RCC_OscConfig+0x36e>
 800228e:	4b5b      	ldr	r3, [pc, #364]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 8002290:	6a1b      	ldr	r3, [r3, #32]
 8002292:	4a5a      	ldr	r2, [pc, #360]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 8002294:	f023 0301 	bic.w	r3, r3, #1
 8002298:	6213      	str	r3, [r2, #32]
 800229a:	4b58      	ldr	r3, [pc, #352]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 800229c:	6a1b      	ldr	r3, [r3, #32]
 800229e:	4a57      	ldr	r2, [pc, #348]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 80022a0:	f023 0304 	bic.w	r3, r3, #4
 80022a4:	6213      	str	r3, [r2, #32]
    /* Check the LSE State */
    if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
 80022a6:	687b      	ldr	r3, [r7, #4]
 80022a8:	68db      	ldr	r3, [r3, #12]
 80022aa:	2b00      	cmp	r3, #0
 80022ac:	d015      	beq.n	80022da <HAL_RCC_OscConfig+0x3a2>
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 80022ae:	f7fe fde3 	bl	8000e78 <HAL_GetTick>
 80022b2:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is ready */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 80022b4:	e00a      	b.n	80022cc <HAL_RCC_OscConfig+0x394>
      {
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 80022b6:	f7fe fddf 	bl	8000e78 <HAL_GetTick>
 80022ba:	4602      	mov	r2, r0
 80022bc:	693b      	ldr	r3, [r7, #16]
 80022be:	1ad3      	subs	r3, r2, r3
 80022c0:	f241 3288 	movw	r2, #5000	; 0x1388
 80022c4:	4293      	cmp	r3, r2
 80022c6:	d901      	bls.n	80022cc <HAL_RCC_OscConfig+0x394>
        {
          return HAL_TIMEOUT;
 80022c8:	2303      	movs	r3, #3
 80022ca:	e0b1      	b.n	8002430 <HAL_RCC_OscConfig+0x4f8>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
 80022cc:	4b4b      	ldr	r3, [pc, #300]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 80022ce:	6a1b      	ldr	r3, [r3, #32]
 80022d0:	f003 0302 	and.w	r3, r3, #2
 80022d4:	2b00      	cmp	r3, #0
 80022d6:	d0ee      	beq.n	80022b6 <HAL_RCC_OscConfig+0x37e>
 80022d8:	e014      	b.n	8002304 <HAL_RCC_OscConfig+0x3cc>
      }
    }
    else
    {
      /* Get Start Tick */
      tickstart = HAL_GetTick();
 80022da:	f7fe fdcd 	bl	8000e78 <HAL_GetTick>
 80022de:	6138      	str	r0, [r7, #16]

      /* Wait till LSE is disabled */
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 80022e0:	e00a      	b.n	80022f8 <HAL_RCC_OscConfig+0x3c0>
      {
        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
 80022e2:	f7fe fdc9 	bl	8000e78 <HAL_GetTick>
 80022e6:	4602      	mov	r2, r0
 80022e8:	693b      	ldr	r3, [r7, #16]
 80022ea:	1ad3      	subs	r3, r2, r3
 80022ec:	f241 3288 	movw	r2, #5000	; 0x1388
 80022f0:	4293      	cmp	r3, r2
 80022f2:	d901      	bls.n	80022f8 <HAL_RCC_OscConfig+0x3c0>
        {
          return HAL_TIMEOUT;
 80022f4:	2303      	movs	r3, #3
 80022f6:	e09b      	b.n	8002430 <HAL_RCC_OscConfig+0x4f8>
      while (__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
 80022f8:	4b40      	ldr	r3, [pc, #256]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 80022fa:	6a1b      	ldr	r3, [r3, #32]
 80022fc:	f003 0302 	and.w	r3, r3, #2
 8002300:	2b00      	cmp	r3, #0
 8002302:	d1ee      	bne.n	80022e2 <HAL_RCC_OscConfig+0x3aa>
        }
      }
    }

    /* Require to disable power clock if necessary */
    if (pwrclkchanged == SET)
 8002304:	7dfb      	ldrb	r3, [r7, #23]
 8002306:	2b01      	cmp	r3, #1
 8002308:	d105      	bne.n	8002316 <HAL_RCC_OscConfig+0x3de>
    {
      __HAL_RCC_PWR_CLK_DISABLE();
 800230a:	4b3c      	ldr	r3, [pc, #240]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 800230c:	69db      	ldr	r3, [r3, #28]
 800230e:	4a3b      	ldr	r2, [pc, #236]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 8002310:	f023 5380 	bic.w	r3, r3, #268435456	; 0x10000000
 8002314:	61d3      	str	r3, [r2, #28]

#endif /* RCC_CR_PLL2ON */
  /*-------------------------------- PLL Configuration -----------------------*/
  /* Check the parameters */
  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
 8002316:	687b      	ldr	r3, [r7, #4]
 8002318:	69db      	ldr	r3, [r3, #28]
 800231a:	2b00      	cmp	r3, #0
 800231c:	f000 8087 	beq.w	800242e <HAL_RCC_OscConfig+0x4f6>
  {
    /* Check if the PLL is used as system clock or not */
    if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
 8002320:	4b36      	ldr	r3, [pc, #216]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 8002322:	685b      	ldr	r3, [r3, #4]
 8002324:	f003 030c 	and.w	r3, r3, #12
 8002328:	2b08      	cmp	r3, #8
 800232a:	d061      	beq.n	80023f0 <HAL_RCC_OscConfig+0x4b8>
    {
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
 800232c:	687b      	ldr	r3, [r7, #4]
 800232e:	69db      	ldr	r3, [r3, #28]
 8002330:	2b02      	cmp	r3, #2
 8002332:	d146      	bne.n	80023c2 <HAL_RCC_OscConfig+0x48a>
        /* Check the parameters */
        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));

        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 8002334:	4b33      	ldr	r3, [pc, #204]	; (8002404 <HAL_RCC_OscConfig+0x4cc>)
 8002336:	2200      	movs	r2, #0
 8002338:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 800233a:	f7fe fd9d 	bl	8000e78 <HAL_GetTick>
 800233e:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8002340:	e008      	b.n	8002354 <HAL_RCC_OscConfig+0x41c>
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 8002342:	f7fe fd99 	bl	8000e78 <HAL_GetTick>
 8002346:	4602      	mov	r2, r0
 8002348:	693b      	ldr	r3, [r7, #16]
 800234a:	1ad3      	subs	r3, r2, r3
 800234c:	2b02      	cmp	r3, #2
 800234e:	d901      	bls.n	8002354 <HAL_RCC_OscConfig+0x41c>
          {
            return HAL_TIMEOUT;
 8002350:	2303      	movs	r3, #3
 8002352:	e06d      	b.n	8002430 <HAL_RCC_OscConfig+0x4f8>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 8002354:	4b29      	ldr	r3, [pc, #164]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 8002356:	681b      	ldr	r3, [r3, #0]
 8002358:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 800235c:	2b00      	cmp	r3, #0
 800235e:	d1f0      	bne.n	8002342 <HAL_RCC_OscConfig+0x40a>
          }
        }

        /* Configure the HSE prediv factor --------------------------------*/
        /* It can be written only when the PLL is disabled. Not used in PLL source is different than HSE */
        if (RCC_OscInitStruct->PLL.PLLSource == RCC_PLLSOURCE_HSE)
 8002360:	687b      	ldr	r3, [r7, #4]
 8002362:	6a1b      	ldr	r3, [r3, #32]
 8002364:	f5b3 3f80 	cmp.w	r3, #65536	; 0x10000
 8002368:	d108      	bne.n	800237c <HAL_RCC_OscConfig+0x444>
          /* Set PREDIV1 source */
          SET_BIT(RCC->CFGR2, RCC_OscInitStruct->Prediv1Source);
#endif /* RCC_CFGR2_PREDIV1SRC */

          /* Set PREDIV1 Value */
          __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
 800236a:	4b24      	ldr	r3, [pc, #144]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 800236c:	685b      	ldr	r3, [r3, #4]
 800236e:	f423 3200 	bic.w	r2, r3, #131072	; 0x20000
 8002372:	687b      	ldr	r3, [r7, #4]
 8002374:	689b      	ldr	r3, [r3, #8]
 8002376:	4921      	ldr	r1, [pc, #132]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 8002378:	4313      	orrs	r3, r2
 800237a:	604b      	str	r3, [r1, #4]
        }

        /* Configure the main PLL clock source and multiplication factors. */
        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
 800237c:	4b1f      	ldr	r3, [pc, #124]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 800237e:	685b      	ldr	r3, [r3, #4]
 8002380:	f423 1274 	bic.w	r2, r3, #3997696	; 0x3d0000
 8002384:	687b      	ldr	r3, [r7, #4]
 8002386:	6a19      	ldr	r1, [r3, #32]
 8002388:	687b      	ldr	r3, [r7, #4]
 800238a:	6a5b      	ldr	r3, [r3, #36]	; 0x24
 800238c:	430b      	orrs	r3, r1
 800238e:	491b      	ldr	r1, [pc, #108]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 8002390:	4313      	orrs	r3, r2
 8002392:	604b      	str	r3, [r1, #4]
                             RCC_OscInitStruct->PLL.PLLMUL);
        /* Enable the main PLL. */
        __HAL_RCC_PLL_ENABLE();
 8002394:	4b1b      	ldr	r3, [pc, #108]	; (8002404 <HAL_RCC_OscConfig+0x4cc>)
 8002396:	2201      	movs	r2, #1
 8002398:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 800239a:	f7fe fd6d 	bl	8000e78 <HAL_GetTick>
 800239e:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is ready */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
 80023a0:	e008      	b.n	80023b4 <HAL_RCC_OscConfig+0x47c>
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 80023a2:	f7fe fd69 	bl	8000e78 <HAL_GetTick>
 80023a6:	4602      	mov	r2, r0
 80023a8:	693b      	ldr	r3, [r7, #16]
 80023aa:	1ad3      	subs	r3, r2, r3
 80023ac:	2b02      	cmp	r3, #2
 80023ae:	d901      	bls.n	80023b4 <HAL_RCC_OscConfig+0x47c>
          {
            return HAL_TIMEOUT;
 80023b0:	2303      	movs	r3, #3
 80023b2:	e03d      	b.n	8002430 <HAL_RCC_OscConfig+0x4f8>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
 80023b4:	4b11      	ldr	r3, [pc, #68]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 80023b6:	681b      	ldr	r3, [r3, #0]
 80023b8:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 80023bc:	2b00      	cmp	r3, #0
 80023be:	d0f0      	beq.n	80023a2 <HAL_RCC_OscConfig+0x46a>
 80023c0:	e035      	b.n	800242e <HAL_RCC_OscConfig+0x4f6>
        }
      }
      else
      {
        /* Disable the main PLL. */
        __HAL_RCC_PLL_DISABLE();
 80023c2:	4b10      	ldr	r3, [pc, #64]	; (8002404 <HAL_RCC_OscConfig+0x4cc>)
 80023c4:	2200      	movs	r2, #0
 80023c6:	601a      	str	r2, [r3, #0]

        /* Get Start Tick */
        tickstart = HAL_GetTick();
 80023c8:	f7fe fd56 	bl	8000e78 <HAL_GetTick>
 80023cc:	6138      	str	r0, [r7, #16]

        /* Wait till PLL is disabled */
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 80023ce:	e008      	b.n	80023e2 <HAL_RCC_OscConfig+0x4aa>
        {
          if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
 80023d0:	f7fe fd52 	bl	8000e78 <HAL_GetTick>
 80023d4:	4602      	mov	r2, r0
 80023d6:	693b      	ldr	r3, [r7, #16]
 80023d8:	1ad3      	subs	r3, r2, r3
 80023da:	2b02      	cmp	r3, #2
 80023dc:	d901      	bls.n	80023e2 <HAL_RCC_OscConfig+0x4aa>
          {
            return HAL_TIMEOUT;
 80023de:	2303      	movs	r3, #3
 80023e0:	e026      	b.n	8002430 <HAL_RCC_OscConfig+0x4f8>
        while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
 80023e2:	4b06      	ldr	r3, [pc, #24]	; (80023fc <HAL_RCC_OscConfig+0x4c4>)
 80023e4:	681b      	ldr	r3, [r3, #0]
 80023e6:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 80023ea:	2b00      	cmp	r3, #0
 80023ec:	d1f0      	bne.n	80023d0 <HAL_RCC_OscConfig+0x498>
 80023ee:	e01e      	b.n	800242e <HAL_RCC_OscConfig+0x4f6>
      }
    }
    else
    {
      /* Check if there is a request to disable the PLL used as System clock source */
      if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
 80023f0:	687b      	ldr	r3, [r7, #4]
 80023f2:	69db      	ldr	r3, [r3, #28]
 80023f4:	2b01      	cmp	r3, #1
 80023f6:	d107      	bne.n	8002408 <HAL_RCC_OscConfig+0x4d0>
      {
        return HAL_ERROR;
 80023f8:	2301      	movs	r3, #1
 80023fa:	e019      	b.n	8002430 <HAL_RCC_OscConfig+0x4f8>
 80023fc:	40021000 	.word	0x40021000
 8002400:	40007000 	.word	0x40007000
 8002404:	42420060 	.word	0x42420060
      }
      else
      {
        /* Do not return HAL_ERROR if request repeats the current configuration */
        pll_config = RCC->CFGR;
 8002408:	4b0b      	ldr	r3, [pc, #44]	; (8002438 <HAL_RCC_OscConfig+0x500>)
 800240a:	685b      	ldr	r3, [r3, #4]
 800240c:	60fb      	str	r3, [r7, #12]
        if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 800240e:	68fb      	ldr	r3, [r7, #12]
 8002410:	f403 3280 	and.w	r2, r3, #65536	; 0x10000
 8002414:	687b      	ldr	r3, [r7, #4]
 8002416:	6a1b      	ldr	r3, [r3, #32]
 8002418:	429a      	cmp	r2, r3
 800241a:	d106      	bne.n	800242a <HAL_RCC_OscConfig+0x4f2>
            (READ_BIT(pll_config, RCC_CFGR_PLLMULL) != RCC_OscInitStruct->PLL.PLLMUL))
 800241c:	68fb      	ldr	r3, [r7, #12]
 800241e:	f403 1270 	and.w	r2, r3, #3932160	; 0x3c0000
 8002422:	687b      	ldr	r3, [r7, #4]
 8002424:	6a5b      	ldr	r3, [r3, #36]	; 0x24
        if ((READ_BIT(pll_config, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
 8002426:	429a      	cmp	r2, r3
 8002428:	d001      	beq.n	800242e <HAL_RCC_OscConfig+0x4f6>
        {
          return HAL_ERROR;
 800242a:	2301      	movs	r3, #1
 800242c:	e000      	b.n	8002430 <HAL_RCC_OscConfig+0x4f8>
        }
      }
    }
  }

  return HAL_OK;
 800242e:	2300      	movs	r3, #0
}
 8002430:	4618      	mov	r0, r3
 8002432:	3718      	adds	r7, #24
 8002434:	46bd      	mov	sp, r7
 8002436:	bd80      	pop	{r7, pc}
 8002438:	40021000 	.word	0x40021000

0800243c <HAL_RCC_ClockConfig>:
  *         You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
  *         currently used as system clock source.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
{
 800243c:	b580      	push	{r7, lr}
 800243e:	b084      	sub	sp, #16
 8002440:	af00      	add	r7, sp, #0
 8002442:	6078      	str	r0, [r7, #4]
 8002444:	6039      	str	r1, [r7, #0]
  uint32_t tickstart;

  /* Check Null pointer */
  if (RCC_ClkInitStruct == NULL)
 8002446:	687b      	ldr	r3, [r7, #4]
 8002448:	2b00      	cmp	r3, #0
 800244a:	d101      	bne.n	8002450 <HAL_RCC_ClockConfig+0x14>
  {
    return HAL_ERROR;
 800244c:	2301      	movs	r3, #1
 800244e:	e0d0      	b.n	80025f2 <HAL_RCC_ClockConfig+0x1b6>
  must be correctly programmed according to the frequency of the CPU clock
    (HCLK) of the device. */

#if defined(FLASH_ACR_LATENCY)
  /* Increasing the number of wait states because of higher CPU frequency */
  if (FLatency > __HAL_FLASH_GET_LATENCY())
 8002450:	4b6a      	ldr	r3, [pc, #424]	; (80025fc <HAL_RCC_ClockConfig+0x1c0>)
 8002452:	681b      	ldr	r3, [r3, #0]
 8002454:	f003 0307 	and.w	r3, r3, #7
 8002458:	683a      	ldr	r2, [r7, #0]
 800245a:	429a      	cmp	r2, r3
 800245c:	d910      	bls.n	8002480 <HAL_RCC_ClockConfig+0x44>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 800245e:	4b67      	ldr	r3, [pc, #412]	; (80025fc <HAL_RCC_ClockConfig+0x1c0>)
 8002460:	681b      	ldr	r3, [r3, #0]
 8002462:	f023 0207 	bic.w	r2, r3, #7
 8002466:	4965      	ldr	r1, [pc, #404]	; (80025fc <HAL_RCC_ClockConfig+0x1c0>)
 8002468:	683b      	ldr	r3, [r7, #0]
 800246a:	4313      	orrs	r3, r2
 800246c:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
 800246e:	4b63      	ldr	r3, [pc, #396]	; (80025fc <HAL_RCC_ClockConfig+0x1c0>)
 8002470:	681b      	ldr	r3, [r3, #0]
 8002472:	f003 0307 	and.w	r3, r3, #7
 8002476:	683a      	ldr	r2, [r7, #0]
 8002478:	429a      	cmp	r2, r3
 800247a:	d001      	beq.n	8002480 <HAL_RCC_ClockConfig+0x44>
  {
    return HAL_ERROR;
 800247c:	2301      	movs	r3, #1
 800247e:	e0b8      	b.n	80025f2 <HAL_RCC_ClockConfig+0x1b6>
  }
}

#endif /* FLASH_ACR_LATENCY */
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
 8002480:	687b      	ldr	r3, [r7, #4]
 8002482:	681b      	ldr	r3, [r3, #0]
 8002484:	f003 0302 	and.w	r3, r3, #2
 8002488:	2b00      	cmp	r3, #0
 800248a:	d020      	beq.n	80024ce <HAL_RCC_ClockConfig+0x92>
  {
    /* Set the highest APBx dividers in order to ensure that we do not go through
    a non-spec phase whatever we decrease or increase HCLK. */
    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 800248c:	687b      	ldr	r3, [r7, #4]
 800248e:	681b      	ldr	r3, [r3, #0]
 8002490:	f003 0304 	and.w	r3, r3, #4
 8002494:	2b00      	cmp	r3, #0
 8002496:	d005      	beq.n	80024a4 <HAL_RCC_ClockConfig+0x68>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
 8002498:	4b59      	ldr	r3, [pc, #356]	; (8002600 <HAL_RCC_ClockConfig+0x1c4>)
 800249a:	685b      	ldr	r3, [r3, #4]
 800249c:	4a58      	ldr	r2, [pc, #352]	; (8002600 <HAL_RCC_ClockConfig+0x1c4>)
 800249e:	f443 63e0 	orr.w	r3, r3, #1792	; 0x700
 80024a2:	6053      	str	r3, [r2, #4]
    }

    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 80024a4:	687b      	ldr	r3, [r7, #4]
 80024a6:	681b      	ldr	r3, [r3, #0]
 80024a8:	f003 0308 	and.w	r3, r3, #8
 80024ac:	2b00      	cmp	r3, #0
 80024ae:	d005      	beq.n	80024bc <HAL_RCC_ClockConfig+0x80>
    {
      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
 80024b0:	4b53      	ldr	r3, [pc, #332]	; (8002600 <HAL_RCC_ClockConfig+0x1c4>)
 80024b2:	685b      	ldr	r3, [r3, #4]
 80024b4:	4a52      	ldr	r2, [pc, #328]	; (8002600 <HAL_RCC_ClockConfig+0x1c4>)
 80024b6:	f443 5360 	orr.w	r3, r3, #14336	; 0x3800
 80024ba:	6053      	str	r3, [r2, #4]
    }

    /* Set the new HCLK clock divider */
    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
 80024bc:	4b50      	ldr	r3, [pc, #320]	; (8002600 <HAL_RCC_ClockConfig+0x1c4>)
 80024be:	685b      	ldr	r3, [r3, #4]
 80024c0:	f023 02f0 	bic.w	r2, r3, #240	; 0xf0
 80024c4:	687b      	ldr	r3, [r7, #4]
 80024c6:	689b      	ldr	r3, [r3, #8]
 80024c8:	494d      	ldr	r1, [pc, #308]	; (8002600 <HAL_RCC_ClockConfig+0x1c4>)
 80024ca:	4313      	orrs	r3, r2
 80024cc:	604b      	str	r3, [r1, #4]
  }

  /*------------------------- SYSCLK Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
 80024ce:	687b      	ldr	r3, [r7, #4]
 80024d0:	681b      	ldr	r3, [r3, #0]
 80024d2:	f003 0301 	and.w	r3, r3, #1
 80024d6:	2b00      	cmp	r3, #0
 80024d8:	d040      	beq.n	800255c <HAL_RCC_ClockConfig+0x120>
  {
    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));

    /* HSE is selected as System Clock Source */
    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
 80024da:	687b      	ldr	r3, [r7, #4]
 80024dc:	685b      	ldr	r3, [r3, #4]
 80024de:	2b01      	cmp	r3, #1
 80024e0:	d107      	bne.n	80024f2 <HAL_RCC_ClockConfig+0xb6>
    {
      /* Check the HSE ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
 80024e2:	4b47      	ldr	r3, [pc, #284]	; (8002600 <HAL_RCC_ClockConfig+0x1c4>)
 80024e4:	681b      	ldr	r3, [r3, #0]
 80024e6:	f403 3300 	and.w	r3, r3, #131072	; 0x20000
 80024ea:	2b00      	cmp	r3, #0
 80024ec:	d115      	bne.n	800251a <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 80024ee:	2301      	movs	r3, #1
 80024f0:	e07f      	b.n	80025f2 <HAL_RCC_ClockConfig+0x1b6>
      }
    }
    /* PLL is selected as System Clock Source */
    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
 80024f2:	687b      	ldr	r3, [r7, #4]
 80024f4:	685b      	ldr	r3, [r3, #4]
 80024f6:	2b02      	cmp	r3, #2
 80024f8:	d107      	bne.n	800250a <HAL_RCC_ClockConfig+0xce>
    {
      /* Check the PLL ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
 80024fa:	4b41      	ldr	r3, [pc, #260]	; (8002600 <HAL_RCC_ClockConfig+0x1c4>)
 80024fc:	681b      	ldr	r3, [r3, #0]
 80024fe:	f003 7300 	and.w	r3, r3, #33554432	; 0x2000000
 8002502:	2b00      	cmp	r3, #0
 8002504:	d109      	bne.n	800251a <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 8002506:	2301      	movs	r3, #1
 8002508:	e073      	b.n	80025f2 <HAL_RCC_ClockConfig+0x1b6>
    }
    /* HSI is selected as System Clock Source */
    else
    {
      /* Check the HSI ready flag */
      if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
 800250a:	4b3d      	ldr	r3, [pc, #244]	; (8002600 <HAL_RCC_ClockConfig+0x1c4>)
 800250c:	681b      	ldr	r3, [r3, #0]
 800250e:	f003 0302 	and.w	r3, r3, #2
 8002512:	2b00      	cmp	r3, #0
 8002514:	d101      	bne.n	800251a <HAL_RCC_ClockConfig+0xde>
      {
        return HAL_ERROR;
 8002516:	2301      	movs	r3, #1
 8002518:	e06b      	b.n	80025f2 <HAL_RCC_ClockConfig+0x1b6>
      }
    }
    __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
 800251a:	4b39      	ldr	r3, [pc, #228]	; (8002600 <HAL_RCC_ClockConfig+0x1c4>)
 800251c:	685b      	ldr	r3, [r3, #4]
 800251e:	f023 0203 	bic.w	r2, r3, #3
 8002522:	687b      	ldr	r3, [r7, #4]
 8002524:	685b      	ldr	r3, [r3, #4]
 8002526:	4936      	ldr	r1, [pc, #216]	; (8002600 <HAL_RCC_ClockConfig+0x1c4>)
 8002528:	4313      	orrs	r3, r2
 800252a:	604b      	str	r3, [r1, #4]

    /* Get Start Tick */
    tickstart = HAL_GetTick();
 800252c:	f7fe fca4 	bl	8000e78 <HAL_GetTick>
 8002530:	60f8      	str	r0, [r7, #12]

    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 8002532:	e00a      	b.n	800254a <HAL_RCC_ClockConfig+0x10e>
    {
      if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
 8002534:	f7fe fca0 	bl	8000e78 <HAL_GetTick>
 8002538:	4602      	mov	r2, r0
 800253a:	68fb      	ldr	r3, [r7, #12]
 800253c:	1ad3      	subs	r3, r2, r3
 800253e:	f241 3288 	movw	r2, #5000	; 0x1388
 8002542:	4293      	cmp	r3, r2
 8002544:	d901      	bls.n	800254a <HAL_RCC_ClockConfig+0x10e>
      {
        return HAL_TIMEOUT;
 8002546:	2303      	movs	r3, #3
 8002548:	e053      	b.n	80025f2 <HAL_RCC_ClockConfig+0x1b6>
    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
 800254a:	4b2d      	ldr	r3, [pc, #180]	; (8002600 <HAL_RCC_ClockConfig+0x1c4>)
 800254c:	685b      	ldr	r3, [r3, #4]
 800254e:	f003 020c 	and.w	r2, r3, #12
 8002552:	687b      	ldr	r3, [r7, #4]
 8002554:	685b      	ldr	r3, [r3, #4]
 8002556:	009b      	lsls	r3, r3, #2
 8002558:	429a      	cmp	r2, r3
 800255a:	d1eb      	bne.n	8002534 <HAL_RCC_ClockConfig+0xf8>
    }
  }

#if defined(FLASH_ACR_LATENCY)
  /* Decreasing the number of wait states because of lower CPU frequency */
  if (FLatency < __HAL_FLASH_GET_LATENCY())
 800255c:	4b27      	ldr	r3, [pc, #156]	; (80025fc <HAL_RCC_ClockConfig+0x1c0>)
 800255e:	681b      	ldr	r3, [r3, #0]
 8002560:	f003 0307 	and.w	r3, r3, #7
 8002564:	683a      	ldr	r2, [r7, #0]
 8002566:	429a      	cmp	r2, r3
 8002568:	d210      	bcs.n	800258c <HAL_RCC_ClockConfig+0x150>
  {
    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
    __HAL_FLASH_SET_LATENCY(FLatency);
 800256a:	4b24      	ldr	r3, [pc, #144]	; (80025fc <HAL_RCC_ClockConfig+0x1c0>)
 800256c:	681b      	ldr	r3, [r3, #0]
 800256e:	f023 0207 	bic.w	r2, r3, #7
 8002572:	4922      	ldr	r1, [pc, #136]	; (80025fc <HAL_RCC_ClockConfig+0x1c0>)
 8002574:	683b      	ldr	r3, [r7, #0]
 8002576:	4313      	orrs	r3, r2
 8002578:	600b      	str	r3, [r1, #0]

    /* Check that the new number of wait states is taken into account to access the Flash
    memory by reading the FLASH_ACR register */
    if (__HAL_FLASH_GET_LATENCY() != FLatency)
 800257a:	4b20      	ldr	r3, [pc, #128]	; (80025fc <HAL_RCC_ClockConfig+0x1c0>)
 800257c:	681b      	ldr	r3, [r3, #0]
 800257e:	f003 0307 	and.w	r3, r3, #7
 8002582:	683a      	ldr	r2, [r7, #0]
 8002584:	429a      	cmp	r2, r3
 8002586:	d001      	beq.n	800258c <HAL_RCC_ClockConfig+0x150>
  {
    return HAL_ERROR;
 8002588:	2301      	movs	r3, #1
 800258a:	e032      	b.n	80025f2 <HAL_RCC_ClockConfig+0x1b6>
  }
}
#endif /* FLASH_ACR_LATENCY */

/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
 800258c:	687b      	ldr	r3, [r7, #4]
 800258e:	681b      	ldr	r3, [r3, #0]
 8002590:	f003 0304 	and.w	r3, r3, #4
 8002594:	2b00      	cmp	r3, #0
 8002596:	d008      	beq.n	80025aa <HAL_RCC_ClockConfig+0x16e>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
 8002598:	4b19      	ldr	r3, [pc, #100]	; (8002600 <HAL_RCC_ClockConfig+0x1c4>)
 800259a:	685b      	ldr	r3, [r3, #4]
 800259c:	f423 62e0 	bic.w	r2, r3, #1792	; 0x700
 80025a0:	687b      	ldr	r3, [r7, #4]
 80025a2:	68db      	ldr	r3, [r3, #12]
 80025a4:	4916      	ldr	r1, [pc, #88]	; (8002600 <HAL_RCC_ClockConfig+0x1c4>)
 80025a6:	4313      	orrs	r3, r2
 80025a8:	604b      	str	r3, [r1, #4]
  }

  /*-------------------------- PCLK2 Configuration ---------------------------*/
  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
 80025aa:	687b      	ldr	r3, [r7, #4]
 80025ac:	681b      	ldr	r3, [r3, #0]
 80025ae:	f003 0308 	and.w	r3, r3, #8
 80025b2:	2b00      	cmp	r3, #0
 80025b4:	d009      	beq.n	80025ca <HAL_RCC_ClockConfig+0x18e>
  {
    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
 80025b6:	4b12      	ldr	r3, [pc, #72]	; (8002600 <HAL_RCC_ClockConfig+0x1c4>)
 80025b8:	685b      	ldr	r3, [r3, #4]
 80025ba:	f423 5260 	bic.w	r2, r3, #14336	; 0x3800
 80025be:	687b      	ldr	r3, [r7, #4]
 80025c0:	691b      	ldr	r3, [r3, #16]
 80025c2:	00db      	lsls	r3, r3, #3
 80025c4:	490e      	ldr	r1, [pc, #56]	; (8002600 <HAL_RCC_ClockConfig+0x1c4>)
 80025c6:	4313      	orrs	r3, r2
 80025c8:	604b      	str	r3, [r1, #4]
  }

  /* Update the SystemCoreClock global variable */
  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos];
 80025ca:	f000 f821 	bl	8002610 <HAL_RCC_GetSysClockFreq>
 80025ce:	4602      	mov	r2, r0
 80025d0:	4b0b      	ldr	r3, [pc, #44]	; (8002600 <HAL_RCC_ClockConfig+0x1c4>)
 80025d2:	685b      	ldr	r3, [r3, #4]
 80025d4:	091b      	lsrs	r3, r3, #4
 80025d6:	f003 030f 	and.w	r3, r3, #15
 80025da:	490a      	ldr	r1, [pc, #40]	; (8002604 <HAL_RCC_ClockConfig+0x1c8>)
 80025dc:	5ccb      	ldrb	r3, [r1, r3]
 80025de:	fa22 f303 	lsr.w	r3, r2, r3
 80025e2:	4a09      	ldr	r2, [pc, #36]	; (8002608 <HAL_RCC_ClockConfig+0x1cc>)
 80025e4:	6013      	str	r3, [r2, #0]

  /* Configure the source of time base considering new system clocks settings*/
  HAL_InitTick(uwTickPrio);
 80025e6:	4b09      	ldr	r3, [pc, #36]	; (800260c <HAL_RCC_ClockConfig+0x1d0>)
 80025e8:	681b      	ldr	r3, [r3, #0]
 80025ea:	4618      	mov	r0, r3
 80025ec:	f7fe fc02 	bl	8000df4 <HAL_InitTick>

  return HAL_OK;
 80025f0:	2300      	movs	r3, #0
}
 80025f2:	4618      	mov	r0, r3
 80025f4:	3710      	adds	r7, #16
 80025f6:	46bd      	mov	sp, r7
 80025f8:	bd80      	pop	{r7, pc}
 80025fa:	bf00      	nop
 80025fc:	40022000 	.word	0x40022000
 8002600:	40021000 	.word	0x40021000
 8002604:	08004938 	.word	0x08004938
 8002608:	20000010 	.word	0x20000010
 800260c:	20000014 	.word	0x20000014

08002610 <HAL_RCC_GetSysClockFreq>:
  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
  *
  * @retval SYSCLK frequency
  */
uint32_t HAL_RCC_GetSysClockFreq(void)
{
 8002610:	b480      	push	{r7}
 8002612:	b087      	sub	sp, #28
 8002614:	af00      	add	r7, sp, #0
#else
  static const uint8_t aPredivFactorTable[2U] = {1, 2};
#endif /*RCC_CFGR2_PREDIV1*/

#endif
  uint32_t tmpreg = 0U, prediv = 0U, pllclk = 0U, pllmul = 0U;
 8002616:	2300      	movs	r3, #0
 8002618:	60fb      	str	r3, [r7, #12]
 800261a:	2300      	movs	r3, #0
 800261c:	60bb      	str	r3, [r7, #8]
 800261e:	2300      	movs	r3, #0
 8002620:	617b      	str	r3, [r7, #20]
 8002622:	2300      	movs	r3, #0
 8002624:	607b      	str	r3, [r7, #4]
  uint32_t sysclockfreq = 0U;
 8002626:	2300      	movs	r3, #0
 8002628:	613b      	str	r3, [r7, #16]
#if defined(RCC_CFGR2_PREDIV1SRC)
  uint32_t prediv2 = 0U, pll2mul = 0U;
#endif /*RCC_CFGR2_PREDIV1SRC*/

  tmpreg = RCC->CFGR;
 800262a:	4b1e      	ldr	r3, [pc, #120]	; (80026a4 <HAL_RCC_GetSysClockFreq+0x94>)
 800262c:	685b      	ldr	r3, [r3, #4]
 800262e:	60fb      	str	r3, [r7, #12]

  /* Get SYSCLK source -------------------------------------------------------*/
  switch (tmpreg & RCC_CFGR_SWS)
 8002630:	68fb      	ldr	r3, [r7, #12]
 8002632:	f003 030c 	and.w	r3, r3, #12
 8002636:	2b04      	cmp	r3, #4
 8002638:	d002      	beq.n	8002640 <HAL_RCC_GetSysClockFreq+0x30>
 800263a:	2b08      	cmp	r3, #8
 800263c:	d003      	beq.n	8002646 <HAL_RCC_GetSysClockFreq+0x36>
 800263e:	e027      	b.n	8002690 <HAL_RCC_GetSysClockFreq+0x80>
  {
    case RCC_SYSCLKSOURCE_STATUS_HSE:  /* HSE used as system clock */
    {
      sysclockfreq = HSE_VALUE;
 8002640:	4b19      	ldr	r3, [pc, #100]	; (80026a8 <HAL_RCC_GetSysClockFreq+0x98>)
 8002642:	613b      	str	r3, [r7, #16]
      break;
 8002644:	e027      	b.n	8002696 <HAL_RCC_GetSysClockFreq+0x86>
    }
    case RCC_SYSCLKSOURCE_STATUS_PLLCLK:  /* PLL used as system clock */
    {
      pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMULL) >> RCC_CFGR_PLLMULL_Pos];
 8002646:	68fb      	ldr	r3, [r7, #12]
 8002648:	0c9b      	lsrs	r3, r3, #18
 800264a:	f003 030f 	and.w	r3, r3, #15
 800264e:	4a17      	ldr	r2, [pc, #92]	; (80026ac <HAL_RCC_GetSysClockFreq+0x9c>)
 8002650:	5cd3      	ldrb	r3, [r2, r3]
 8002652:	607b      	str	r3, [r7, #4]
      if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI_DIV2)
 8002654:	68fb      	ldr	r3, [r7, #12]
 8002656:	f403 3380 	and.w	r3, r3, #65536	; 0x10000
 800265a:	2b00      	cmp	r3, #0
 800265c:	d010      	beq.n	8002680 <HAL_RCC_GetSysClockFreq+0x70>
      {
#if defined(RCC_CFGR2_PREDIV1)
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV1) >> RCC_CFGR2_PREDIV1_Pos];
#else
        prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR & RCC_CFGR_PLLXTPRE) >> RCC_CFGR_PLLXTPRE_Pos];
 800265e:	4b11      	ldr	r3, [pc, #68]	; (80026a4 <HAL_RCC_GetSysClockFreq+0x94>)
 8002660:	685b      	ldr	r3, [r3, #4]
 8002662:	0c5b      	lsrs	r3, r3, #17
 8002664:	f003 0301 	and.w	r3, r3, #1
 8002668:	4a11      	ldr	r2, [pc, #68]	; (80026b0 <HAL_RCC_GetSysClockFreq+0xa0>)
 800266a:	5cd3      	ldrb	r3, [r2, r3]
 800266c:	60bb      	str	r3, [r7, #8]
        {
          pllclk = pllclk / 2;
        }
#else
        /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV1 * PLLMUL */
        pllclk = (uint32_t)((HSE_VALUE  * pllmul) / prediv);
 800266e:	687b      	ldr	r3, [r7, #4]
 8002670:	4a0d      	ldr	r2, [pc, #52]	; (80026a8 <HAL_RCC_GetSysClockFreq+0x98>)
 8002672:	fb03 f202 	mul.w	r2, r3, r2
 8002676:	68bb      	ldr	r3, [r7, #8]
 8002678:	fbb2 f3f3 	udiv	r3, r2, r3
 800267c:	617b      	str	r3, [r7, #20]
 800267e:	e004      	b.n	800268a <HAL_RCC_GetSysClockFreq+0x7a>
#endif /*RCC_CFGR2_PREDIV1SRC*/
      }
      else
      {
        /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
        pllclk = (uint32_t)((HSI_VALUE >> 1) * pllmul);
 8002680:	687b      	ldr	r3, [r7, #4]
 8002682:	4a0c      	ldr	r2, [pc, #48]	; (80026b4 <HAL_RCC_GetSysClockFreq+0xa4>)
 8002684:	fb02 f303 	mul.w	r3, r2, r3
 8002688:	617b      	str	r3, [r7, #20]
      }
      sysclockfreq = pllclk;
 800268a:	697b      	ldr	r3, [r7, #20]
 800268c:	613b      	str	r3, [r7, #16]
      break;
 800268e:	e002      	b.n	8002696 <HAL_RCC_GetSysClockFreq+0x86>
    }
    case RCC_SYSCLKSOURCE_STATUS_HSI:  /* HSI used as system clock source */
    default: /* HSI used as system clock */
    {
      sysclockfreq = HSI_VALUE;
 8002690:	4b05      	ldr	r3, [pc, #20]	; (80026a8 <HAL_RCC_GetSysClockFreq+0x98>)
 8002692:	613b      	str	r3, [r7, #16]
      break;
 8002694:	bf00      	nop
    }
  }
  return sysclockfreq;
 8002696:	693b      	ldr	r3, [r7, #16]
}
 8002698:	4618      	mov	r0, r3
 800269a:	371c      	adds	r7, #28
 800269c:	46bd      	mov	sp, r7
 800269e:	bc80      	pop	{r7}
 80026a0:	4770      	bx	lr
 80026a2:	bf00      	nop
 80026a4:	40021000 	.word	0x40021000
 80026a8:	007a1200 	.word	0x007a1200
 80026ac:	08004950 	.word	0x08004950
 80026b0:	08004960 	.word	0x08004960
 80026b4:	003d0900 	.word	0x003d0900

080026b8 <HAL_RCC_GetHCLKFreq>:
  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency
  *         and updated within this function
  * @retval HCLK frequency
  */
uint32_t HAL_RCC_GetHCLKFreq(void)
{
 80026b8:	b480      	push	{r7}
 80026ba:	af00      	add	r7, sp, #0
  return SystemCoreClock;
 80026bc:	4b02      	ldr	r3, [pc, #8]	; (80026c8 <HAL_RCC_GetHCLKFreq+0x10>)
 80026be:	681b      	ldr	r3, [r3, #0]
}
 80026c0:	4618      	mov	r0, r3
 80026c2:	46bd      	mov	sp, r7
 80026c4:	bc80      	pop	{r7}
 80026c6:	4770      	bx	lr
 80026c8:	20000010 	.word	0x20000010

080026cc <HAL_RCC_GetPCLK1Freq>:
  * @note   Each time PCLK1 changes, this function must be called to update the
  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
  * @retval PCLK1 frequency
  */
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
 80026cc:	b580      	push	{r7, lr}
 80026ce:	af00      	add	r7, sp, #0
  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
  return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos]);
 80026d0:	f7ff fff2 	bl	80026b8 <HAL_RCC_GetHCLKFreq>
 80026d4:	4602      	mov	r2, r0
 80026d6:	4b05      	ldr	r3, [pc, #20]	; (80026ec <HAL_RCC_GetPCLK1Freq+0x20>)
 80026d8:	685b      	ldr	r3, [r3, #4]
 80026da:	0a1b      	lsrs	r3, r3, #8
 80026dc:	f003 0307 	and.w	r3, r3, #7
 80026e0:	4903      	ldr	r1, [pc, #12]	; (80026f0 <HAL_RCC_GetPCLK1Freq+0x24>)
 80026e2:	5ccb      	ldrb	r3, [r1, r3]
 80026e4:	fa22 f303 	lsr.w	r3, r2, r3
}
 80026e8:	4618      	mov	r0, r3
 80026ea:	bd80      	pop	{r7, pc}
 80026ec:	40021000 	.word	0x40021000
 80026f0:	08004948 	.word	0x08004948

080026f4 <RCC_Delay>:
  * @brief  This function provides delay (in milliseconds) based on CPU cycles method.
  * @param  mdelay: specifies the delay time length, in milliseconds.
  * @retval None
  */
static void RCC_Delay(uint32_t mdelay)
{
 80026f4:	b480      	push	{r7}
 80026f6:	b085      	sub	sp, #20
 80026f8:	af00      	add	r7, sp, #0
 80026fa:	6078      	str	r0, [r7, #4]
  __IO uint32_t Delay = mdelay * (SystemCoreClock / 8U / 1000U);
 80026fc:	4b0a      	ldr	r3, [pc, #40]	; (8002728 <RCC_Delay+0x34>)
 80026fe:	681b      	ldr	r3, [r3, #0]
 8002700:	4a0a      	ldr	r2, [pc, #40]	; (800272c <RCC_Delay+0x38>)
 8002702:	fba2 2303 	umull	r2, r3, r2, r3
 8002706:	0a5b      	lsrs	r3, r3, #9
 8002708:	687a      	ldr	r2, [r7, #4]
 800270a:	fb02 f303 	mul.w	r3, r2, r3
 800270e:	60fb      	str	r3, [r7, #12]
  do
  {
    __NOP();
 8002710:	bf00      	nop
  }
  while (Delay --);
 8002712:	68fb      	ldr	r3, [r7, #12]
 8002714:	1e5a      	subs	r2, r3, #1
 8002716:	60fa      	str	r2, [r7, #12]
 8002718:	2b00      	cmp	r3, #0
 800271a:	d1f9      	bne.n	8002710 <RCC_Delay+0x1c>
}
 800271c:	bf00      	nop
 800271e:	bf00      	nop
 8002720:	3714      	adds	r7, #20
 8002722:	46bd      	mov	sp, r7
 8002724:	bc80      	pop	{r7}
 8002726:	4770      	bx	lr
 8002728:	20000010 	.word	0x20000010
 800272c:	10624dd3 	.word	0x10624dd3

08002730 <__itoa>:
 8002730:	1e93      	subs	r3, r2, #2
 8002732:	2b22      	cmp	r3, #34	; 0x22
 8002734:	b510      	push	{r4, lr}
 8002736:	460c      	mov	r4, r1
 8002738:	d904      	bls.n	8002744 <__itoa+0x14>
 800273a:	2300      	movs	r3, #0
 800273c:	461c      	mov	r4, r3
 800273e:	700b      	strb	r3, [r1, #0]
 8002740:	4620      	mov	r0, r4
 8002742:	bd10      	pop	{r4, pc}
 8002744:	2a0a      	cmp	r2, #10
 8002746:	d109      	bne.n	800275c <__itoa+0x2c>
 8002748:	2800      	cmp	r0, #0
 800274a:	da07      	bge.n	800275c <__itoa+0x2c>
 800274c:	232d      	movs	r3, #45	; 0x2d
 800274e:	700b      	strb	r3, [r1, #0]
 8002750:	2101      	movs	r1, #1
 8002752:	4240      	negs	r0, r0
 8002754:	4421      	add	r1, r4
 8002756:	f000 f805 	bl	8002764 <__utoa>
 800275a:	e7f1      	b.n	8002740 <__itoa+0x10>
 800275c:	2100      	movs	r1, #0
 800275e:	e7f9      	b.n	8002754 <__itoa+0x24>

08002760 <itoa>:
 8002760:	f7ff bfe6 	b.w	8002730 <__itoa>

08002764 <__utoa>:
 8002764:	b5f0      	push	{r4, r5, r6, r7, lr}
 8002766:	b08b      	sub	sp, #44	; 0x2c
 8002768:	4605      	mov	r5, r0
 800276a:	460b      	mov	r3, r1
 800276c:	466e      	mov	r6, sp
 800276e:	4c1d      	ldr	r4, [pc, #116]	; (80027e4 <__utoa+0x80>)
 8002770:	f104 0c20 	add.w	ip, r4, #32
 8002774:	4637      	mov	r7, r6
 8002776:	6820      	ldr	r0, [r4, #0]
 8002778:	6861      	ldr	r1, [r4, #4]
 800277a:	3408      	adds	r4, #8
 800277c:	c703      	stmia	r7!, {r0, r1}
 800277e:	4564      	cmp	r4, ip
 8002780:	463e      	mov	r6, r7
 8002782:	d1f7      	bne.n	8002774 <__utoa+0x10>
 8002784:	7921      	ldrb	r1, [r4, #4]
 8002786:	6820      	ldr	r0, [r4, #0]
 8002788:	7139      	strb	r1, [r7, #4]
 800278a:	1e91      	subs	r1, r2, #2
 800278c:	2922      	cmp	r1, #34	; 0x22
 800278e:	6038      	str	r0, [r7, #0]
 8002790:	f04f 0100 	mov.w	r1, #0
 8002794:	d904      	bls.n	80027a0 <__utoa+0x3c>
 8002796:	7019      	strb	r1, [r3, #0]
 8002798:	460b      	mov	r3, r1
 800279a:	4618      	mov	r0, r3
 800279c:	b00b      	add	sp, #44	; 0x2c
 800279e:	bdf0      	pop	{r4, r5, r6, r7, pc}
 80027a0:	1e58      	subs	r0, r3, #1
 80027a2:	4684      	mov	ip, r0
 80027a4:	fbb5 f7f2 	udiv	r7, r5, r2
 80027a8:	fb02 5617 	mls	r6, r2, r7, r5
 80027ac:	3628      	adds	r6, #40	; 0x28
 80027ae:	446e      	add	r6, sp
 80027b0:	f816 6c28 	ldrb.w	r6, [r6, #-40]
 80027b4:	460c      	mov	r4, r1
 80027b6:	f80c 6f01 	strb.w	r6, [ip, #1]!
 80027ba:	462e      	mov	r6, r5
 80027bc:	42b2      	cmp	r2, r6
 80027be:	463d      	mov	r5, r7
 80027c0:	f101 0101 	add.w	r1, r1, #1
 80027c4:	d9ee      	bls.n	80027a4 <__utoa+0x40>
 80027c6:	2200      	movs	r2, #0
 80027c8:	545a      	strb	r2, [r3, r1]
 80027ca:	1919      	adds	r1, r3, r4
 80027cc:	1aa5      	subs	r5, r4, r2
 80027ce:	42aa      	cmp	r2, r5
 80027d0:	dae3      	bge.n	800279a <__utoa+0x36>
 80027d2:	f810 5f01 	ldrb.w	r5, [r0, #1]!
 80027d6:	780e      	ldrb	r6, [r1, #0]
 80027d8:	3201      	adds	r2, #1
 80027da:	7006      	strb	r6, [r0, #0]
 80027dc:	f801 5901 	strb.w	r5, [r1], #-1
 80027e0:	e7f4      	b.n	80027cc <__utoa+0x68>
 80027e2:	bf00      	nop
 80027e4:	08004962 	.word	0x08004962

080027e8 <memset>:
 80027e8:	4603      	mov	r3, r0
 80027ea:	4402      	add	r2, r0
 80027ec:	4293      	cmp	r3, r2
 80027ee:	d100      	bne.n	80027f2 <memset+0xa>
 80027f0:	4770      	bx	lr
 80027f2:	f803 1b01 	strb.w	r1, [r3], #1
 80027f6:	e7f9      	b.n	80027ec <memset+0x4>

080027f8 <__libc_init_array>:
 80027f8:	b570      	push	{r4, r5, r6, lr}
 80027fa:	2600      	movs	r6, #0
 80027fc:	4d0c      	ldr	r5, [pc, #48]	; (8002830 <__libc_init_array+0x38>)
 80027fe:	4c0d      	ldr	r4, [pc, #52]	; (8002834 <__libc_init_array+0x3c>)
 8002800:	1b64      	subs	r4, r4, r5
 8002802:	10a4      	asrs	r4, r4, #2
 8002804:	42a6      	cmp	r6, r4
 8002806:	d109      	bne.n	800281c <__libc_init_array+0x24>
 8002808:	f000 f81a 	bl	8002840 <_init>
 800280c:	2600      	movs	r6, #0
 800280e:	4d0a      	ldr	r5, [pc, #40]	; (8002838 <__libc_init_array+0x40>)
 8002810:	4c0a      	ldr	r4, [pc, #40]	; (800283c <__libc_init_array+0x44>)
 8002812:	1b64      	subs	r4, r4, r5
 8002814:	10a4      	asrs	r4, r4, #2
 8002816:	42a6      	cmp	r6, r4
 8002818:	d105      	bne.n	8002826 <__libc_init_array+0x2e>
 800281a:	bd70      	pop	{r4, r5, r6, pc}
 800281c:	f855 3b04 	ldr.w	r3, [r5], #4
 8002820:	4798      	blx	r3
 8002822:	3601      	adds	r6, #1
 8002824:	e7ee      	b.n	8002804 <__libc_init_array+0xc>
 8002826:	f855 3b04 	ldr.w	r3, [r5], #4
 800282a:	4798      	blx	r3
 800282c:	3601      	adds	r6, #1
 800282e:	e7f2      	b.n	8002816 <__libc_init_array+0x1e>
 8002830:	08004988 	.word	0x08004988
 8002834:	08004988 	.word	0x08004988
 8002838:	08004988 	.word	0x08004988
 800283c:	0800498c 	.word	0x0800498c

08002840 <_init>:
 8002840:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 8002842:	bf00      	nop
 8002844:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8002846:	bc08      	pop	{r3}
 8002848:	469e      	mov	lr, r3
 800284a:	4770      	bx	lr

0800284c <_fini>:
 800284c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
 800284e:	bf00      	nop
 8002850:	bcf8      	pop	{r3, r4, r5, r6, r7}
 8002852:	bc08      	pop	{r3}
 8002854:	469e      	mov	lr, r3
 8002856:	4770      	bx	lr
